Wafer tester and wafer testing method and system

1 . A wafer testing method, comprising:

assigning a plurality of testing programs to a batch of wafers in a same wafer testing stage, wherein each of the plurality of testing programs comprises testing algorithms configured to measure parameters of the batch of wafers;

setting a plurality sets of testing conditions for the plurality of testing programs; and

testing at least one of the batch of wafers by executing a corresponding one of the plurality of testing programs according to a corresponding one of the plurality sets of testing conditions,

wherein assigning the plurality of testing programs to the batch of wafers comprises:

assigning a first testing program of the plurality of testing programs to a first wafer of the batch of wafers; and

assigning a second testing program of the plurality of testing programs to a second wafer of the batch of wafers, wherein the second testing program is different from the first testing program,

wherein the first testing program comprises a first plurality of testing algorithms, the second testing program comprises a second plurality of testing algorithms, and the first plurality of testing algorithms and the second plurality of testing algorithms are different from each other.

2 . The wafer testing method of claim 1 , wherein

assigning the first testing program to the first wafer comprises assigning at least one of the first plurality of testing algorithms to the first wafer; and

assigning the second testing program to the second wafer comprises assigning at least one of the second plurality of testing algorithms to the second wafer.

3 . The wafer testing method of claim 2 , wherein testing the at least one of the batch of wafers by executing the corresponding one of the plurality of testing programs comprises:

measuring at least one first parameter of the first wafer by executing the at least one of the first plurality of testing algorithms; and

measuring at least one second parameter of the second wafer by executing the at least one of the second plurality of testing algorithms.

4 . The wafer testing method claim 1 , wherein setting the plurality sets of testing conditions for the plurality of testing programs comprises:

setting a first set of testing conditions for the first testing program; and

setting a second set of testing conditions for the second testing program.

5 . The wafer testing method claim 4 , wherein testing the at least one of the batch of wafers by executing the corresponding one of the plurality of testing programs according to the corresponding one of the plurality sets of testing conditions comprises:

testing the first wafer by executing the first testing program according to the first set of testing conditions; and

testing the second wafer by executing the second testing program according to the second set of testing conditions.

6 . The wafer testing method of claim 1 , further comprising:

assigning a plurality sets of testing sites to the batch of wafers, wherein each of the plurality sets of testing sites indicates at least one die of one of the batch of wafers.

7 . A wafer tester, comprising:

a non-transitory computer-readable medium, configured to store a plurality of testing programs, a plurality sets of testing conditions, and a plurality sets of testing sites;

a processor, coupled to the non-transitory computer-readable medium, the processor configured to assign a first testing program of the plurality of testing programs to a first wafer of a batch of wafers and assign a second testing program of the plurality of testing programs to a second wafer of the batch of wafers in a same wafer testing stage, wherein the second testing program is different from the first testing program; and

a test head, coupled to the processor;

wherein, in response to the processor executing the plurality of testing programs, the test head is configured to test the batch of wafers according to the plurality of testing programs, the plurality sets of testing conditions, and the plurality sets of testing sites;

each of the plurality of testing programs comprises testing algorithms configured to measure parameters of the batch of wafers, the first testing program comprises a first plurality of testing algorithms, the second testing program comprises a second plurality of testing algorithms, and the first plurality of testing algorithms and the second plurality of testing algorithms are different from each other;

each of the plurality sets of testing conditions corresponds to one of the plurality of testing programs; and

each of the plurality sets of testing sites indicates at least one die of one of the batch of wafers.

8 . The wafer tester of claim 7 , wherein the test head is further configured to test the first wafer according to the first testing program and test the second wafer according to the second testing program.

9 . The wafer tester of claim 7 , wherein the processor is configured to assign the plurality sets of testing sites to the batch of wafers.

10 . A wafer testing system, comprising:

a tester, comprising:

a non-transitory computer-readable medium configured to store a plurality of testing programs, a plurality sets of testing conditions, and a plurality sets of testing sites;

a processor, coupled to the non-transitory computer-readable medium and configured to assign the plurality of testing programs to a batch of wafers, comprising assigning a first testing program of the plurality of testing programs to a first wafer of the batch of wafers and assigning a second testing program of the plurality of testing programs to a second wafer of the batch of wafers in a same wafer testing stage, wherein the second testing program is different from the first testing program; and

a test head, coupled to the processor; and

a prober, comprising a probe card, wherein the probe card is coupled to the test head and configured to create an electrical path between the test head and at least one of the batch of wafers;

wherein the test head is configured to test the at least one of the batch of wafers through the probe card according to a corresponding one of the plurality of testing programs;

each of the plurality of testing programs comprises a plurality of testing algorithms configured to measure parameters of the batch of wafers, the first testing program comprises a first plurality of testing algorithms, the second testing program comprises a second plurality of testing algorithms, and the first plurality of testing algorithms and the second plurality of testing algorithms are different from each other;

each of the plurality sets of testing conditions corresponds to one of the plurality of testing programs; and

each of the plurality sets of testing sites indicates at least one die of one of the batch of wafers.

11 . The wafer testing system of claim 10 , wherein the test head is further configured to measure at least one first parameter of the first wafer according to the first testing program and measure at least one second parameter of the second wafer according to the second testing program.

12 . The wafer testing system of claim 10 , wherein the processor is configured to assign a first set of testing sites of the plurality sets of testing sites to a first wafer of the batch of wafers and assign a second set of testing sites of the plurality sets of testing sites to a second wafer of the batch of wafers.

13 . The wafer testing system of claim 12 , wherein the test head is further configured to measure at least one first parameter of the first wafer according to the first set of testing sites and measure at least one second parameter of the second wafer according to the second set of testing sites.