Semiconductor package
According to one aspect of the present disclosure, a semiconductor package is provided. The semiconductor package may include a first semiconductor chip. The semiconductor package may include at least one second semiconductor chip. The semiconductor package may include a switch protection circuit having a first end connected with the first semiconductor chip and a second end connected with each of the at least one second semiconductor chip. When the semiconductor package is undergoing a charged device model (CDM) discharge, the switch protection circuit may be in an off state to disconnect the first semiconductor chip and the second semiconductor chip.
1 . A semiconductor package, comprising:
a first semiconductor chip;
at least one second semiconductor chip; and
a switch protection circuit having a first end connected with the first semiconductor chip, a second end connected with each of the at least one second semiconductor chip, and a control end configured to receive a control signal for controlling the switch protection circuit to be in an off state or an on state,
wherein:
a state of the control signal is determined based on whether a pin of the semiconductor package is undergoing a charged device model (CDM) discharge, the control signal comprises a first state indicating a CDM discharge at the pin and a second state indicating a normal operation of the semiconductor package; and
when the switch protection circuit is fed with the control signal of the first state indicative of a CDM discharge, the switch protection circuit is in an off state to disconnect the first semiconductor chip and the at least one second semiconductor chip.
2 . The semiconductor package of claim 1 , wherein when the switch protection circuit is fed with the control signal of the second state indicating that the semiconductor package is in a normal operation, the switch protection circuit is in an on state to connect the first semiconductor chip and the at least one second semiconductor chip.
3 . The semiconductor package of claim 1 , wherein:
the switch protection circuit is disposed in the first semiconductor chip and comprises a first sub-circuit,
a first end of the first sub-circuit is connected with a first node in the first semiconductor chip,
a second end of the first sub-circuit is connected with a second node in the first semiconductor chip,
a control end of the first sub-circuit is fed with a first control signal, the control end of the first sub-circuit being the control end of the switch protection circuit, and the first control signal being the control signal,
the first sub-circuit is in an off state when being fed with the first control signal of a first state, or the first sub-circuit is in an on state when being fed with the first control signal of a second state,
when the first sub-circuit is in the off state, the first semiconductor chip and the at least one second semiconductor chip are disconnected, and
when the first sub-circuit is in the on state, the first semiconductor chip and the at least one second semiconductor chip are connected.
4 . The semiconductor package of claim 3 , wherein:
the switch protection circuit further comprises a second sub-circuit,
the second sub-circuit comprises a first capacitive element having a first end connected between the second end of the first sub-circuit and the second node in the first semiconductor chip and a second end connected with a third node in the first semiconductor chip, and
the control end of the first sub-circuit is connected between the second end of the first capacitive element and the third node.
5 . The semiconductor package of claim 3 , wherein:
the switch protection circuit further comprises a second sub-circuit,
the second sub-circuit comprises a second capacitive element having a first end connected between the second end of the first sub-circuit and the second node in the first semiconductor chip and a second end connected with a first node in a second semiconductor chip of the at least one second semiconductor chip, and
the control end of the first sub-circuit is connected between the second end of the second capacitive element and the first node in the second semiconductor chip.
6 . The semiconductor package of claim 4 , wherein:
the second sub-circuit further comprises a first resistive element having a first end connected with the third node in the first semiconductor chip and a second end connected with the second end of the first capacitive element, and
the control end of the first sub-circuit is connected between the second end of the first capacitive element and the second end of the first resistive element.
7 . The semiconductor package of claim 5 , wherein:
the second sub-circuit further comprises a second resistive element having a first end connected with the first node in the second semiconductor chip and a second end connected with the second end of the second capacitive element, and
the control end of the first sub-circuit is connected between the second end of the second capacitive element and the second end of the second resistive element.
8 . The semiconductor package of claim 3 , wherein the first sub-circuit comprises a first N-type metal oxide semiconductor (NMOS) transistor.
9 . The semiconductor package of claim 6 , wherein:
the first resistive element comprises at least one resistor connected in series,
the first capacitive element comprises at least one capacitor connected in series, and
a product of a resistance value of the at least one resistor and a capacitance value of the at least one capacitor is in a range of 1 ns-1 μs.
10 . The semiconductor package of claim 7 , wherein:
the second resistive element comprises at least one resistor connected in series,
the second capacitive element comprises at least one capacitor connected in series, and
a product of a resistance value of the at least one resistor and a capacitance value of the at least one capacitor is in a range of 1 ns-1 μs.
11 . The semiconductor package of claim 6 , wherein:
the first node in the first semiconductor chip is connected with a grounding pad in the first semiconductor chip,
the second node in the first semiconductor chip is connected with a grounding pin of the first semiconductor chip, and
the third node in the first semiconductor chip is connected with a power supply pad in the first semiconductor chip.
12 . The semiconductor package of claim 7 , wherein:
the first node in the first semiconductor chip is connected with a grounding pad in the first semiconductor chip,
the second node in the first semiconductor chip is connected with a grounding pin of the first semiconductor chip, and
the first node in the second semiconductor chip is connected with a power supply pad in the second semiconductor chip.
13 . The semiconductor package of claim 1 , wherein:
the switch protection circuit is disposed in each of the at least one second semiconductor chip and comprises a third sub-circuit,
a first end of the third sub-circuit is connected with a second node in the at least one second semiconductor chip,
a second end of the third sub-circuit is connected with a third node in the at least one second semiconductor chip,
a control end of the third sub-circuit is fed with a second control signal, the control end of the third sub-circuit being the control end of the switch protection circuit, and the second control signal being the control signal,
the third sub-circuit is in an off state when being fed with the second control signal of a first state, or the third sub-circuit is in an on state when being fed with the second control signal of a second state,
when the third sub-circuit is in an off state, the first semiconductor chip and the at least one second semiconductor chip are disconnected, and
when the third sub-circuit is in an on state, the first semiconductor chip and the at least one second semiconductor chip are connected.
14 . The semiconductor package of claim 13 , wherein:
the switch protection circuit further comprises a fourth sub-circuit,
the fourth sub-circuit comprises a third capacitive element having a first end connected between the second end of the third sub-circuit and the third node in the at least one second semiconductor chip and a second end connected with a first node in the at least one second semiconductor chip, and
the control end of the third sub-circuit is connected between the second end of the third capacitive element and the first node in the at least one second semiconductor chip.
15 . The semiconductor package of claim 13 , wherein:
the switch protection circuit further comprises a fourth sub-circuit,
the fourth sub-circuit comprises a fourth capacitive element having a first end connected between the second end of the third sub-circuit and the third node in the at least one second semiconductor chip and a second end connected with a third node in the first semiconductor chip, and
the control end of the third sub-circuit is connected between the second end of the fourth capacitive element and the third node in the first semiconductor chip.
16 . The semiconductor package of claim 14 , wherein:
the fourth sub-circuit further comprises a third resistive element having a first end connected with the first node in the at least one second semiconductor chip and a second end connected with the second end of the third capacitive element, and
the control end of the third sub-circuit is connected between the second end of the third capacitive element and the second end of the third resistive element.
17 . The semiconductor package of claim 15 , wherein:
the fourth sub-circuit further comprises a fourth resistive element having a first end connected with the third node in the first semiconductor chip and a second end connected with the second end of the fourth capacitive element, and
the control end of the third sub-circuit is connected between the second end of the fourth capacitive element and the second end of the fourth resistive element.
18 . The semiconductor package of claim 13 , wherein the third sub-circuit comprises a second N-type metal oxide semiconductor (NMOS) transistor.
19 . A semiconductor package, comprising:
a package housing provided with a first pin that is susceptible to a charged device model (CDM) discharge;
a first semiconductor chip in the package housing; and
at least one second semiconductor chip in the package housing, each being connected with the first semiconductor chip via a N-type metal oxide semiconductor (NMOS) transistor,
wherein the NMOS transistor is disposed in the first semiconductor chip or in each of the at least one second semiconductor chip,
wherein a control end of the NMOS transistor is fed with a control signal for controlling the NMOS transistor to be in an off state or an on state,
wherein a state of the control signal is determined based on whether the first pin is undergoing the CDM discharge,
wherein the semiconductor package further comprises a capacitive element having a first end connected with a second end of the NMOS transistor, and a second end connected with a node of one of the first semiconductor chip and the at least one second semiconductor chip, and
wherein the control end of the NMOS transistor is connected between the second end of the capacitive element and the node.
20 . An integrated circuit (IC) chip, comprising:
a semiconductor package, comprising:
a first semiconductor chip;
at least one second semiconductor chip; and
a switch protection circuit having a first end connected with the first semiconductor chip, a second end connected with each of the at least one second semiconductor chip, and a control end configured to receive a control signal for controlling the switch protection circuit to be in an off state or an on state,
wherein:
a state of the control signal is determined based on whether a pin of the semiconductor package is undergoing a charged device model (CDM) discharge, the control signal comprises a first state indicating a CDM discharge at the pin and a second state indicating a normal operation of the semiconductor package; and
when the switch protection circuit is fed with the control signal of the first state indicative of a CDM discharge, the switch protection circuit is in an off state to disconnect the first semiconductor chip and the at least one second semiconductor chip.