IP Library › Granted Patent US 12710522
Granted Patent B2
US 12710522 · App. 16/925,435 · Granted Aug 18, 2026

Apparatus

Inventor: Masaaki Ishitsuka (Nasushiobara, JP)
Assignee: CANON MEDICAL SYSTEMS CORPORATION
G01S7/52025A61B8/5246A61B8/5269A61B8/54G01S7/5202
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Quick Facts
Patent No.
US 12710522
App. No.
16/925,435
Granted
Aug 18, 2026
Kind
B2
Abstract

An apparatus according to the embodiment includes a first delay circuit, a second delay circuit, and processing circuitry. The first delay circuit delays an ultrasound signal in a first channel using a plurality of capacitors. The second delay circuit delays an ultrasound signal in a second channel using a plurality of capacitors. The processing circuitry make a first write start position in which writing the ultrasound signal in the capacitor in the first delay circuit is started and a second write start position in which writing the ultrasound signal in the capacitor in the second delay circuit is started different from each other.

Claims (38)

1 . An apparatus, comprising:

a first delay circuit that delays an ultrasound signal in a first channel using a first plurality of capacitors, the first delay circuit corresponding to the first channel;

a second delay circuit that delays an ultrasound signal in a second channel, which is different from the first channel, using a second plurality of capacitors, the second delay circuit corresponding to the second channel;

a third delay circuit that delays an ultrasound signal in a third channel using a third plurality of capacitors;

a fourth delay circuit that delays an ultrasound signal in a fourth channel using a fourth plurality of capacitors;

processing circuitry configured to make a first write start position in which writing the ultrasound signal in a capacitor in the first delay circuit is started and a second write start position in which writing the ultrasound signal in a capacitor in the second delay circuit is started different from each other by inputting a control signal which has a periodicity, to each of the first delay circuit and the second delay circuit; and

summing circuitry configured to generate a summing signal by summing the ultrasound signal that is delayed by the first delay circuit and the ultrasound signal that is delayed by the second delay circuit,

wherein the processing circuitry is further configured to make the first write start position and the second write start position different from each other such that a periodic noise resulting from the periodicity of the control signal and contained in the summing signal is smaller than a periodic noise resulting from the periodicity of the control signal and contained in the ultrasound signal that is delayed by the first delay circuit and in the ultrasound signal that is delayed by the second delay circuit, and

wherein the processing circuitry is further configured to make the first write start position, the second write start position, a third write start position in which writing the ultrasound signal in a capacitor in the third delay circuit is started, and a fourth write start position in which writing the ultrasound signal in a capacitor in the fourth delay circuit is started different from one another such that a phase difference between the ultrasound signal that is delayed by the third delay circuit and the ultrasound signal that is delayed by the fourth delay circuit is 180 degrees and a phase difference between the ultrasound signal that is delayed by the first delay circuit and the ultrasound signal that is delayed by the third delay circuit and a phase difference between the ultrasound signal that is delayed by the second delay circuit and the ultrasound signal that is delayed by the fourth delay circuit are 90 degrees.

2 . The apparatus according to claim 1 , wherein the processing circuitry is further configured to make the first write start position and the second write start position different from each other based on a number of the first plurality of capacitors contained in the first delay circuit or a number of the second plurality of capacitors contained in the second delay circuit.

3 . The apparatus according to claim 1 , wherein the summing circuitry is further configured to generate an additional summing signal by summing (A) the summing signal generated by summing the ultrasound signal that is delayed by the first delay circuit and the ultrasound signal that is delayed by the second delay circuit, and (B) a signal generated by summing the ultrasound signal that is delayed by the third delay circuit and the ultrasound signal that is delayed by the fourth delay circuit.

4 . The apparatus according to claim 1 , wherein

the first delay circuit periodically writes the ultrasound signal in the capacitor of the first delay circuit, and

the second delay circuit periodically writes the ultrasound signal in the capacitor of the second delay circuit.

5 . The apparatus according to claim 4 , wherein

the first delay circuit periodically reads the ultrasound signal from the capacitor of the first delay circuit, and

the second delay circuit periodically reads the ultrasound signal from the capacitor of the second delay circuit.

6 . The apparatus according to claim 1 , wherein

the first delay circuit periodically writes the ultrasound signal in the capacitor of the first delay circuit,

the second delay circuit periodically writes the ultrasound signal in the capacitor of the second delay circuit,

the third delay circuit periodically writes the ultrasound signal in the capacitor of the third delay circuit, and

the fourth delay circuit periodically writes the ultrasound signal in the capacitor of the fourth delay circuit.

7 . The apparatus according to claim 1 , wherein a number of the first plurality of capacitors that are used by the first delay circuit and a number of the second plurality of capacitors that are used by the second delay circuit are equal to each other.

8 . The apparatus according to claim 1 , wherein the apparatus is an ultrasound probe.

9 . The apparatus according to claim 1 , wherein the apparatus is an ultrasound diagnostic apparatus.

10 . The apparatus according to claim 1 , wherein the processing circuitry is further configured to make a first read position in which the ultrasound signal is read at a first time from the capacitor of the first delay circuit and a second read position in which the ultrasound signal is read at a second time from the capacitor of the second delay circuit different from each other by making the first write start position and the second write start position different from each other, the first and second times being identical.

11 . The apparatus according to claim 1 , wherein the processing circuitry is further configured to make the first write start position and the second write start position different from each other based on a delay of the first delay circuit and a delay of the second delay circuit.

12 . The apparatus according to claim 1 , wherein the processing circuitry is further configured to make the first write start position, the second write start position, the third write start position, and the fourth write start position different from one another based on a delay of the first delay circuit, a delay of the second delay circuit, a delay of the third delay circuit, and a delay of the fourth delay circuit.

13 . An apparatus, comprising:

a first delay circuit that delays an ultrasound signal in a first channel using a first plurality of capacitors, the first delay circuit corresponding to the first channel;

a second delay circuit that delays an ultrasound signal in a second channel, which is different from the first channel, using a second plurality of capacitors, the second delay circuit corresponding to the second channel;

processing circuitry configured to make a first write start position in which writing the ultrasound signal in a capacitor in the first delay circuit is started and a second write start position in which writing the ultrasound signal in a capacitor in the second delay circuit is started different from each other; and

summing circuitry configured to generate a summing signal by summing the ultrasound signal that is delayed by the first delay circuit and the ultrasound signal that is delayed by the second delay circuit,

wherein the processing circuitry is further configured to make the first write start position and the second write start position different from each other such that a noise contained in the summing signal is smaller than a noise contained in the ultrasound signal that is delayed by the first delay circuit and in the ultrasound signal that is delayed by the second delay circuit,

wherein the apparatus further comprises

a third delay circuit that delays an ultrasound signal in a third channel using a third plurality of capacitors; and

a fourth delay circuit that delays an ultrasound signal in a fourth channel using a fourth plurality of capacitors; and

wherein the processing circuitry is further configured to make the first write start position, the second write start position, a third write start position in which writing the ultrasound signal in a capacitor in the third delay circuit is started, and a fourth write start position in which writing the ultrasound signal in a capacitor in the fourth delay circuit is started different from one another such that a phase difference between the ultrasound signal that is delayed by the third delay circuit and the ultrasound signal that is delayed by the fourth delay circuit is 180 degrees and a phase difference between the ultrasound signal that is delayed by the first delay circuit and the ultrasound signal that is delayed by the third delay circuit and a phase difference between the ultrasound signal that is delayed by the second delay circuit and the ultrasound signal that is delayed by the fourth delay circuit are 90 degrees.