IP Library Granted Patent US 12710573
Granted Patent B2
US 12710573 · App. 18/314,953 · Granted Aug 18, 2026

Photoresist loading solutions for flat optics fabrication

Inventors: Sage Toko Garrett Doshay (Saratoga, CA); Rutger Meyer Timmerman Thijssen (Sunnyvale, CA); Ludovic Godet (Sunnyvale, CA); Chien-An Chen (San Jose, CA); Pinkesh Rohit Shah (San Jose, CA)
Assignee: Applied Materials, Inc.
G02B5/20G02B2207/101
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Quick Facts
Patent No.
US 12710573
App. No.
18/314,953
Granted
Aug 18, 2026
Kind
B2
Abstract

Embodiments of the present disclosure relate to methods for fabricating optical devices. One embodiment of the method includes disposing a structure material layer on a surface of a substrate and disposing a patterned photoresist over the structure material layer. The patterned photoresist has at least one device portion and at least one auxiliary portion. Each device portion and each auxiliary portion exposes unmasked portions of the structure material layer. The unmasked portions of structure material layer corresponding to each device portion and each auxiliary portion are etched. The etching the unmasked portions forms at least one optical device having device structures corresponding to the unmasked portions of at least one device portion and at least one auxiliary region having auxiliary structures corresponding to the unmasked portions of at least one auxiliary portion.

Claims (49)

1 . A method, comprising:

disposing a structure material layer on a surface of a substrate;

forming a patterned photoresist over the structure material layer, the patterned photoresist having:

at least one device portion; and

at least one auxiliary portion, wherein each device portion and each auxiliary portion exposes unmasked portions of the structure material layer; and

etching the unmasked portions of structure material layer corresponding to each device portion and each auxiliary portion, wherein the etching the unmasked portions forms:

at least one optical device having one or more arrays of nanostructures disposed on or integral with a surface of a substrate, each of the nanostructures having:

a device critical dimension defined by a width of the nanostructures; and

a device gap defined as a distance between adjacent nanostructures; and

an intermediate region surrounding each optical device, the intermediate region exposing the surface of the substrate, the intermediate region extending a distance greater than the device critical dimension and the device gap, the intermediate region void of nanostructures.

2 . The method of claim 1 , wherein the device critical dimension is less than 1000 nanometers (nm).

3 . The method of claim 1 , wherein the at least one auxiliary portion has a dark-field mask disposed on or integral with the surface of the substrate.

4 . The method of claim 3 , wherein the dark-field mask is at least one of a photoresist or hardmask disposed over an auxiliary structure disposed on the surface of the substrate.

5 . The method of claim 4 , wherein the hardmask includes at least one of chromium (Cr), silver (Ag), silicon nitride (Si3N4), silicon dioxide (SiO2), titanium nitride (TiN), or carbon (C) containing materials.

6 . The method of claim 4 , wherein the nanostructures and the auxiliary structure consist of a same material.

7 . The method of claim 1 , wherein the intermediate region surrounding each optical device is equal in size.

8 . The method of claim 1 , wherein the intermediate region surrounding each optical device is inconsistent in size.

9 . The method of claim 1 , wherein the nanostructures comprise one or more of titanium dioxide (TiO2), zinc oxide (ZnO), tin dioxide (SnO2), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), cadmium stannate (tin oxide) (CTO), zinc stannate (tin oxide) (SnZnO3), silicon nitride (Si3N4), niobium oxide (Nb 2 O 5 ), or silicon containing materials.

10 . A method, comprising:

disposing a structure material layer on a surface of a substrate;

forming a patterned photoresist over the structure material layer, the patterned photoresist having:

at least one device portion; and

at least one auxiliary portion, wherein each device portion of the at least one device portion and each auxiliary portion of the at least one auxiliary portion exposes unmasked portions of the structure material layer; and

etching the unmasked portions of the structure material layer corresponding to the each device portion and the each auxiliary portion, wherein the etching the unmasked portions forms:

at least one optical device having one or more arrays of device structures corresponding to each device portion disposed on or integral with a surface of the substrate, wherein each device structure comprises:

a device critical dimension defined by a width of the device structures the device critical dimension less than 1000 nanometers (nm); and

a device gap defined as a distance between adjacent device structures; and

the at least one auxiliary portion defined by an intermediate region, the intermediate region disposed around a periphery of each optical device, the at least one auxiliary portion having auxiliary structures corresponding to the each auxiliary portion, the at least one auxiliary portion having a distance greater than a width of the device structures and a width of the auxiliary structures.

11 . The method of claim 10 , wherein a width of the unmasked portions is the same for both the at least one device portion and the at least one auxiliary portion.

12 . The method of claim 11 , wherein a device critical dimension of the device structures is equal to an auxiliary critical dimension of the auxiliary structures.

13 . The method of claim 10 , wherein a width of the unmasked portions of the auxiliary portion is greater than the width of the unmasked portions of the at least one device portion.

14 . The method of claim 13 , wherein an auxiliary critical dimension of the 14 auxiliary structures is greater than a device critical dimension of the device structures.

15 . The method of claim 10 , wherein the structure material layer comprises one or more titanium dioxide (TiO2), zinc oxide (ZnO), tin dioxide (SnO2), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), cadmium stannate (tin oxide) (CTO), zinc stannate (tin oxide) (SnZnO3), silicon nitride (Si3N4) and silicon a-Si containing materials.

16 . The method of claim 10 , wherein the etching the unmasked portions comprises one or more of ion implantation, ion etching, reactive ion etching (RIE), directional RIE, plasma etching, and wet etching.

17 . A method, comprising:

disposing a structure material layer on a surface of a substrate;

forming a patterned photoresist over the structure material layer, the patterned photoresist having:

at least one device portion; and

at least one auxiliary portion, wherein each device portion and each auxiliary portion exposes unmasked portions of the structure material layer; and

etching the unmasked portions of structure material layer corresponding to each device portion and each auxiliary portion, wherein the etching the unmasked portions forms:

at least one optical device having one or more arrays of nanostructures disposed on or integral with a surface of a substrate, each of the nanostructures having:

a device critical dimension defined by a width of the nanostructures, the device critical dimension less than 1000 nanometers (nm); and

a device gap defined as a distance between adjacent nanostructures; and

an auxiliary region defined by an intermediate region disposed around a periphery of each optical device, the intermediate region having a width greater than the device critical dimension and the device gap, the auxiliary region void of nanostructures, the auxiliary region having one or more arrays of auxiliary structures disposed on or integral with the surface of the substrate; each of the auxiliary structures having:

an auxiliary critical dimension defined by a width of the auxiliary structures, the auxiliary critical dimension being smaller than the width of the intermediate region; and

an auxiliary gap defined as a distance between adjacent auxiliary structures, the auxiliary gap being smaller than the width of the intermediate region.

18 . The method of claim 17 , wherein the device critical dimension is less than the auxiliary critical dimension.

19 . The method of claim 17 , wherein the device critical dimension is equal to the auxiliary critical dimension.

20 . The method of claim 17 , wherein at least one of the nanostructures or the auxiliary structures comprise one or more of titanium dioxide (TiO2), zinc oxide (ZnO), tin dioxide (SnO2), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), cadmium stannate (tin oxide) (CTO), zinc stannate (tin oxide) (SnZnO3), silicon nitride (Si3N4), niobium oxide (Nb2O5), or silicon containing materials.