IP Library Granted Patent US 12710778
Granted Patent B2
US 12710778 · App. 18/403,650 · Granted Aug 18, 2026

Adjustable voltage divider circuit and method

Inventor: Motoki Tamura (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
G05F1/575G05F1/565H03K17/0822
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Quick Facts
Patent No.
US 12710778
App. No.
18/403,650
Granted
Aug 18, 2026
Kind
B2
Abstract

A circuit includes a first capacitive device coupled between first and second nodes, a second capacitive device coupled between third and fourth nodes, a first switching device coupled between the first node and a voltage node, a second switching device coupled between the second node and a reference voltage node, a third switching device coupled between the third node and the voltage node, a fourth switching device coupled between the fourth node and the reference voltage node, fifth through eighth switching devices coupled between the respective first through fourth nodes and an output node, and first and second variable capacitance devices including first terminals coupled to either the respective first and third nodes or the respective second and fourth nodes.

Claims (72)

1 . A circuit comprising:

a first capacitive device coupled between first and second nodes;

a second capacitive device coupled between third and fourth nodes;

a first switching device coupled between the first node and a voltage node;

a second switching device coupled between the second node and a reference voltage node;

a third switching device coupled between the third node and the voltage node;

a fourth switching device coupled between the fourth node and the reference voltage node;

fifth through eighth switching devices coupled between the respective first through fourth nodes and an output node; and

first and second variable capacitance devices comprising first terminals directly connected to either the respective first and third nodes or the respective second and fourth nodes.

2 . The circuit of claim 1 , wherein

the first terminals of the first and second variable capacitance devices are directly connected to the respective second and fourth nodes, and

each of the first and second variable capacitance devices comprises a second terminal coupled to the output node.

3 . The circuit of claim 1 , wherein

the first terminals of the first and second variable capacitance devices are directly connected to the respective first and third nodes, and

each of the first and second variable capacitance devices comprises a second terminal coupled to the output node.

4 . The circuit of claim 1 , wherein

each of the first and second variable capacitance devices comprises a second terminal coupled to the reference voltage node.

5 . The circuit of claim 1 , wherein

the first, fourth, sixth, and seventh switching devices are configured to be switched on and off alternatively with the second, third, fifth, and eighth switching devices.

6 . The circuit of claim 5 , wherein

a duty cycle of the first, fourth, sixth, and seventh switching devices being switched on and off alternatively with the second, third, fifth, and eighth switching devices is approximately fifty percent.

7 . The circuit of claim 1 , wherein

the first and second capacitive devices are configured to have a same capacitance value.

8 . The circuit of claim 1 , wherein

the first and second variable capacitance devices are configured to have same variable capacitance values.

9 . The circuit of claim 1 , wherein

each of the first and second variable capacitance devices comprises a parallel arrangement of capacitive devices in series with switching devices.

10 . The circuit of claim 1 , further comprising:

a third capacitive device coupled between the output node and the reference voltage node.

11 . A circuit comprising:

a first capacitive device coupled between first and second nodes;

a second capacitive device coupled between third and fourth nodes;

a first switching device coupled between the first node and a voltage node;

a second switching device coupled between the second node and a reference voltage node;

a third switching device coupled between the third node and the voltage node;

a fourth switching device coupled between the fourth node and the reference voltage node;

fifth through eighth switching devices coupled between the respective first through fourth nodes and an output node; and

first and second variable capacitance devices coupled between the output node and either the respective first and third nodes or the respective second and fourth nodes.

12 . The circuit of claim 11 , wherein the first through eighth switching devices are configured to alternatively couple the output node to the reference node through:

a first parallel arrangement of the first capacitive device and the first variable capacitance device, or

a second parallel arrangement of the second capacitive device and the second variable capacitance device.

13 . The circuit of claim 11 , wherein the first through eighth switching devices are configured to alternatively couple the output node to the voltage node through:

a first parallel arrangement of the first capacitive device and the first variable capacitance device, or

a second parallel arrangement of the second capacitive device and the second variable capacitance device.

14 . The circuit of claim 11 , wherein

the first and second capacitive devices are configured to have a same capacitance value,

the first and second variable capacitance devices are configured to have same variable capacitance values, and

the same capacitance value and the same variable capacitance values have a same order of magnitude.

15 . The circuit of claim 11 , further comprising:

a third capacitive device coupled between the output node and the reference voltage node,

wherein the third capacitance device has a capacitance value at least one order of magnitude greater than capacitance values of the first and second capacitive devices and first and second variable capacitance devices.

16 . A method of operating a circuit, the method comprising:

receiving an input voltage at a voltage node of the circuit, the circuit further comprising:

a first capacitive device coupled between first and second nodes;

a second capacitive device coupled between third and fourth nodes;

a first switching device coupled between the first node and the voltage node;

a second switching device coupled between the second node and a reference voltage node;

a third switching device coupled between the third node and the voltage node;

a fourth switching device coupled between the fourth node and the reference voltage node;

fifth through eighth switching devices coupled between the respective first through fourth nodes and an output node; and

first and second variable capacitance devices comprising first terminals coupled to either the respective first and third nodes or the respective second and fourth nodes; and

alternatively switching the first, fourth, sixth, and seventh switching devices with the second, third, fifth, and eighth switching devices, thereby generating an output voltage on the output node.

17 . The method of claim 16 , wherein the alternatively switching the first, fourth, sixth, and seventh switching devices with the second, third, fifth, and eighth switching devices comprises alternatively coupling the output node to the reference node through:

a first parallel arrangement of the first capacitive device and the first variable capacitance device, or

a second parallel arrangement of the second capacitive device and the second variable capacitance device.

18 . The method of claim 16 , wherein the alternatively switching the first, fourth, sixth, and seventh switching devices with the second, third, fifth, and eighth switching devices comprises alternatively coupling the output node to the voltage node through:

a first parallel arrangement of the first capacitive device and the first variable capacitance device, or

a second parallel arrangement of the second capacitive device and the second variable capacitance device.

19 . The method of claim 16 , further comprising:

measuring the output voltage; and

adjusting a capacitance value of each of the variable capacitance devices in response to the measured output voltage.

20 . The method of claim 19 , wherein the adjusting the capacitance value of each of the variable capacitance devices comprises changing a number of capacitive devices arranged in parallel.