Power management system with timing from an analog soft start circuit
Examples of an apparatus and method for power management are disclosed. In an example, a device includes a charge circuit, a discharge circuit, an undervoltage detection circuit, wherein the charge circuit and the discharge circuit are couplable to a capacitor, and wherein the charge circuit includes an analog soft start circuit, and control logic configured to determine a discharge time of the capacitor in response to a timing signal that is generated in response to a voltage from the analog soft start circuit.
1 . A device comprising:
a charge circuit including an analog soft start circuit that includes a soft start capacitor;
a discharge circuit;
an undervoltage detection circuit, wherein the charge circuit and the discharge circuit are couplable to an output capacitor; and
control logic configured to determine a discharge time interval of the output capacitor in response to a timing signal that is generated in response to a voltage from the analog soft start circuit, wherein the control logic includes an analog timer circuit configured to generate the timing signal, the analog timer circuit including a comparator and a reset switch, wherein the analog timer circuit reuses the soft start capacitor of the analog soft start circuit to generate the timing signal during an ultra-low power mode of the device, wherein the comparator is coupled to the soft start capacitor and to a threshold voltage, and wherein the discharge time interval is a function of the threshold voltage and a capacitance of the soft start capacitor.
2 . The device of claim 1 , wherein the reset switch is configured to discharge the voltage from the soft start capacitor of the analog soft start circuit in response to a timer reset signal that is applied to the reset switch.
3 . The device of claim 1 , wherein the device is integrated into a power management integrated circuit (PMIC).
4 . The device of claim 1 , wherein the device is a power management integrated circuit (PMIC), and the PMIC includes a pin for connection to the output capacitor.
5 . The device of claim 1 , wherein the control logic includes combination logic and latches to control the discharge time interval.
6 . The device of claim 5 , wherein the control logic includes an AND gate configured to receive the timing signal and an undervoltage detection signal from the undervoltage detection circuit.
7 . The device of claim 1 , wherein the control logic includes an AND gate configured to receive the timing signal from the analog timer circuit and an undervoltage detection signal from the undervoltage detection circuit.
8 . The device of claim 7 , wherein the control logic further includes a latch configured to generate an undervoltage fault signal in response to the output of the AND gate.
9 . A power management system comprising:
an output capacitor;
a power management integrated circuit (PMIC) including a charge circuit including an analog soft start circuit that includes a soft start capacitor, a discharge circuit, and an undervoltage detection circuit, wherein the charge circuit and the discharge circuit are coupled to the output capacitor via a pin on the PMIC; and
control logic configured to determine a discharge time interval of the output capacitor in response to a timing signal that is generated in response to a voltage from the analog soft start circuit, wherein the control logic includes an analog timer circuit configured to generate the timing signal, the analog timer circuit including a comparator and a reset switch, wherein the analog timer circuit reuses the soft start capacitor of the analog soft start circuit to generate the timing signal during an ultra-low power mode of the PMIC, wherein the comparator is coupled to the soft start capacitor and to a threshold voltage, and wherein the discharge time interval is a function of the threshold voltage and a capacitance of the soft start capacitor.
10 . The power management system of claim 9 , wherein the reset switch is configured to discharge the voltage from the soft start capacitor of the analog soft start circuit in response to a timer reset signal that is applied to the reset switch.
11 . A method for power management, the method comprising:
generating, while a voltage regulator is in an ultra-low power mode, an undervoltage signal in response to detecting an undervoltage condition at an output of the voltage regulator, wherein the voltage regulator includes a charge circuit including an analog soft start circuit that includes a soft start capacitor; and
discharging, while the voltage regulator is in the ultra-low power mode, the voltage regulator for a discharge time interval that is determined in response to a timing signal that is generated in response to a voltage from the analog soft start circuit of the voltage regulator and the undervoltage signal, wherein an analog timer circuit reuses the soft start capacitor of the analog soft start circuit to generate the timing signal during the ultra-low power mode, the analog timer circuit including a comparator coupled to the soft start capacitor and to a threshold voltage, and a reset switch, and wherein the discharge time interval is a function of the threshold voltage and a capacitance of the soft start capacitor.
12 . The method of claim 11 , wherein generating the timing signal involves comparing the voltage from the soft start capacitor of the analog soft start circuit to the threshold voltage.
13 . The method of claim 11 , wherein the analog timer circuit a timing circuit is coupled to the analog soft start circuit and wherein generating the timing signal involves comparing the voltage from the soft start capacitor of the analog soft start circuit to the threshold voltage at the comparator.
14 . The method of claim 13 , further comprising resetting the voltage of the soft start capacitor of the analog soft start circuit after the discharge time interval has expired.