Bandwidth management of a serial interface
This disclosure is directed to dynamic power management of a device interface based on a desired bandwidth for transporting data by the device interface. A device interface may packetize and transport raw data to a processor core complex or a peripheral device. In different embodiments, the peripheral device or the processor core complex may generate the raw data. The peripheral device and/or the processor core complex may increase or decrease a data bandwidth of the device interface for transporting the data. In different cases, the peripheral device or the processor core complex may dynamically activate and deactivate a different number of data links of the device interface based on dynamically determining the desired bandwidth. The peripheral device and/or the processor core complex may reduce a power consumption of the device interface by dynamically deactivating one or more of the data links based on the desired bandwidth being below the data bandwidth of the activated data links.
1 . A device interface comprising:
a receiver comprising a plurality of reception channels; and
a transmitter comprising a plurality of transmission channels, wherein each transmission channel of the plurality of transmission channels is coupled to a respective reception channel of the plurality of reception channels, wherein the transmitter is configured to:
activate a first number of the plurality of transmission channels from a deactivated state to an activated state; and
change, based on an indication of a second number of the plurality of transmission channels, a number of transmission channels in the activated state at least in part by:
deactivating the first number of the plurality of transmission channels from the activated state to the deactivated state; and
activating the second number of the plurality of transmission channels from the deactivated state to the activated state, wherein the second number of the plurality of transmission channels is different from the first number of the plurality of transmission channels.
2 . The device interface of claim 1 , wherein the transmitter is configured to receive the indication of the second number of the plurality of transmission channels from a processor core complex or a peripheral device coupled thereto, wherein the second number of the transmission channels is associated with a desired bandwidth of the device interface for transporting data output from the processor core complex or the peripheral device.
3 . The device interface of claim 1 , wherein the transmitter is configured to transmit a sleep data sequence or a wakeup data sequence indicative of a second number of the plurality of reception channels from the transmitter, wherein the receiver is configured to deactivate at least a first number of the plurality of reception channels associated with the first number of the plurality of transmission channels from the activated state to the deactivated state based on the sleep data sequence, and activate the second number of the plurality of reception channels based on the wakeup data sequence from the deactivated state to the activated state.
4 . The device interface of claim 3 , wherein the transmitter is configured to transmit the indication of the second number of the plurality of transmission channels to the receiver with a designated data packet before transmitting the sleep data sequence, transmit the indication as part of the sleep data sequence, or transmit the indication as part of the wakeup data sequence.
5 . The device interface of claim 3 , wherein a processor core complex or a peripheral device is configured to transmit the indication of the second number of the plurality of transmission channels using a sideband channel.
6 . The device interface of claim 1 , wherein at least one transmission channel of the plurality of transmission channels remains in the deactivated state after activating the second number of the plurality of transmission channels from the deactivated state to the activated state, wherein the first number of the plurality of transmission channels are configured to output a common-mode voltage, maintain a higher output impedance compared to the second number of the plurality of transmission channels after being activated from the deactivated state to the activated state, maintain a ground voltage of the device interface, or any combination thereof when deactivated from the activated state to the deactivated state.
7 . A device interface comprising:
a transmitter comprising a plurality of transmission channels; and
a receiver comprising a plurality of reception channels, wherein each reception channel of the plurality of reception channels is coupled to a respective transmission channel of the plurality of transmission channels, wherein the receiver is configured to:
activate a first number of the plurality of reception channels from a deactivated state to an activated state; and
change, based on an indication of a second number of the plurality of reception channels, a number of reception channels in the activated state at least in part by:
deactivating the first number of the plurality of reception channels from the activated state to the deactivated state; and
activating the second number of the plurality of reception channels from the deactivated state to the activated state, wherein the second number of the plurality of reception channels is different from the first number of the plurality of reception channels.
8 . The device interface of claim 7 , wherein the second number of the plurality of reception channels are associated with a bandwidth of the device interface for transporting data output from a processor core complex or a peripheral device.
9 . The device interface of claim 7 , wherein each of the plurality of reception channels comprise a first data receiver and a second data receiver, wherein the second data receiver of each of the plurality of reception channels is configured to receive data with a higher frequency compared to a respective first data receiver.
10 . The device interface of claim 9 , wherein the receiver is configured to:
activate the first data receiver of at least a first reception channel of the plurality of reception channels, when the first reception channel is in the deactivated state; and
activate the second data receiver of the first reception channel to activate the first reception channel from the deactivated state to the activated state.
11 . The device interface of claim 7 , wherein the receiver is configured to receive a sleep data sequence and a wakeup data sequence from the transmitter, wherein the receiver is configured to deactivate the first number of the plurality of reception channels from the activated state to the deactivated state based on the sleep data sequence, and activate the second number of the plurality of reception channels from the deactivated state to the activated state based on the wakeup data sequence.
12 . The device interface of claim 7 , wherein the receiver is configured to receive the indication of the second number of the plurality of reception channels from the transmitter with a designated data packet before receiving a sleep data sequence, receive the indication as part of the sleep data sequence, receive the indication as part of a wakeup data sequence, or receive the indication via a sideband channel from the transmitter.
13 . The device interface of claim 7 , wherein the receiver is configured to reduce the number of reception channels in the activated state based on the second number of the plurality of reception channels being less than the first number of the plurality of reception channels, or increase the number of reception channels in the activated state based on the second number of the plurality of reception channels being higher than the first number of the plurality of reception channels.
14 . An electronic device comprising:
a processor core complex;
a peripheral device; and
a device interface coupled to the processor core complex and the peripheral device, wherein the device interface comprises a plurality of data links, wherein the device interface is configured to:
activate a first number of the plurality of data links from a deactivated state to an activated state; and
change, based on an indication of a second number of the plurality of data links, a number of data links in the activated state at least in part by:
deactivating the first number of the plurality of data links from the activated state to the deactivated state; and
activating the second number of the plurality of data links from the deactivated state to the activated state, wherein the second number of the plurality of data links is different from the first number of the plurality of data links.
15 . The electronic device of claim 14 , wherein each data link of the first number of the plurality of data links comprises a transmission channel and a reception channel, wherein:
the transmission channel of each of the plurality of data links is coupled to the processor core complex and the reception channel of each of the plurality of data links is coupled to the peripheral device; or
the transmission channel of each of the plurality of data links is coupled to the peripheral device and the reception channel of each of the plurality of data links is coupled to the processor core complex.
16 . The electronic device of claim 15 , wherein at least one data link of the first number of the plurality of data links remains in the deactivated state after activating the second number of the plurality of data links from the deactivated state to the activated state, wherein the transmission channel of the at least one data link is configured to output a common-mode voltage, maintain a higher output impedance compared to transmission channels of the second number of the plurality of data links after being activated from activated from the deactivated state to the activated state, maintain a ground voltage of the electronic device, or any combination thereof when deactivated from the activated state to the deactivated state.
17 . The electronic device of claim 15 , wherein each reception channel of each of the plurality of data links comprises a first data receiver and a second data receiver, wherein each respective second data receiver is configured to receive data with a higher frequency compared to a respective first data receiver, and wherein the electronic device is configured to:
activate the second data receiver of a first reception channel of the plurality of data links to activate the first reception channel from the deactivated state to the activated state; and
deactivate the second data receiver of the first reception channel to deactivate the first reception channel from the activated state to the deactivated state.
18 . The electronic device of claim 14 , wherein the device interface is configured to reduce the number of data links in the activated state based on the second number of the plurality of data links being less than the first number of the plurality of data links.
19 . The electronic device of claim 14 , wherein the device interface is configured to increase the number of data links in the activated state based on the second number of the plurality of data links being higher than the first number of the plurality of data links.
20 . The electronic device of claim 14 , wherein the device interface is configured to receive the indication of the second number of the plurality of data links with a designated data packet before receiving a sleep data sequence, receive the indication as part of the sleep data sequence, receive the indication as part of a wakeup data sequence, or receive the indication via a sideband channel.