Speculative hint-triggered activation of pages in memory
Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes a computing resource and a memory controller coupled to a memory device. The computing resource selectively generates a hint that includes a target address of a memory request generated by the processor. The hint is sent outside the primary communication fabric to the memory controller. The hint conditionally triggers a data access in the memory device. When no page in a bank targeted by the hint is open, the memory controller processes the hint by opening a target page of the hint without retrieving data. The memory controller drops the hint if there are other pending requests that target the same page or the target page is already open.
1 . A memory controller comprising:
a first interface comprising circuitry configured to receive memory requests via a first path;
a second interface comprising circuitry configured to receive memory requests via a second path different from the first path; and
circuitry configured to:
in response to a memory request received via the first interface, send a memory request to a memory device that causes retrieval of data; and
in response to a memory request received via the second interface, send a memory request to the memory device that does not cause retrieval of data.
2 . The memory controller as recited in claim 1 , wherein the circuitry is configured to send the memory request to the memory device that does not cause retrieval of data, in response to the memory request received via the second interface targeting a memory location that is not open or activated at the memory device.
3 . The memory controller as recited in claim 1 , wherein the memory request sent to the memory device in response to the memory request received via the second interface is configured to prepare a memory location for a subsequent access without retrieving data from the memory location.
4 . The memory controller as recited in claim 3 , wherein preparing the memory location for the subsequent access comprises performing a memory operation that opens or activates a portion of the memory device associated with the memory location, without retrieving data from the memory.
5 . The memory controller as recited in claim 1 , wherein the memory request received via the second interface is an activate only request configured to open a page targeted by the memory request received via the first interface without retrieving or returning data from the page.
6 . The memory controller as recited in claim 1 , wherein the memory request received via the second interface corresponds to a memory location identified as latency-sensitive relative to other memory requests.
7 . The memory controller as recited in claim 1 , wherein in response to receiving a given memory request via the second path, the memory controller is configured to drop the given memory request responsive to a page being targeted by the given memory request being open, wherein dropping the given request comprises discarding the given request without performing any memory operation.
8 . The memory controller as recited in claim 1 , wherein the memory request received via the second interface is received prior to the memory request received via the first interface.
9 . A method comprising:
receiving, by circuitry of a memory controller, memory requests via a first interface; and
receiving, by circuitry of the memory controller, memory requests via a second interface different from the first path interface;
in response to a memory request received via the first interface, sending, by circuitry of the memory controller, a memory request to a memory device that causes retrieval of data; and
in response to a memory request received via the second interface, sending, by circuitry of the memory controller, a memory request to the memory device that does not cause retrieval of data.
10 . The method as recited in claim 9 , further comprising sending the memory request to the memory device that does not cause retrieval of data, in response to the memory request received via the second interface targeting a memory location that is not open or activated at the memory device.
11 . The method as recited in claim 9 , wherein the memory request sent to the memory device in response to the memory request received via the second interface is configured to prepare a memory location for a subsequent access without retrieving data from the memory location.
12 . The method as recited in claim 11 , wherein preparing the memory location for the subsequent access comprises performing a memory operation that opens or activates a portion of the memory device associated with the memory location, without retrieving data from the memory device.
13 . The method as recited in claim 9 , wherein the memory request received via the second interface is an activate only request configured to open a page targeted by the first memory request received via the first interface without retrieving or returning data from the page.
14 . The method as recited in claim 9 , wherein the memory request received via the second interface corresponds to a memory location identified as latency-sensitive relative to other memory requests.
15 . The method as recited in claim 9 , wherein in response to receiving a given memory request via the second interface, the method comprises dropping the given memory request responsive to a page being targeted by the given memory request being open, wherein dropping the given request comprises discarding the given request without performing any memory operation.
16 . The method as recited in claim 9 , further comprising the memory request received via the second interface is received prior to the memory request received via the first interface.
17 . A computing system comprising:
a memory controller coupled to receive memory requests from a processor via at least one of a first path and a second path different from the first path, wherein the memory controller comprises circuitry configured to:
in response to a memory request received via the first interface, send a memory request to a memory device that causes retrieval of data; and
in response to a memory request received via the second interface, send a memory request to the memory device that does not cause retrieval of data.
18 . The computing system as recited in claim 17 , wherein the memory controller is configured to send the memory request to the memory device that does not cause retrieval of data, in response to the memory request received via the second interface targeting a memory location that is not open or activated at the memory device.
19 . The computing system as recited in claim 18 , wherein preparing the memory location for the subsequent access comprises performing a memory operation that opens or activates a portion of the memory device associated with the memory location, without retrieving data from the memory device.
20 . The computing system as recited in claim 17 , wherein the memory request sent to the memory device in response to the memory request received via the second interface is configured to prepare a memory location for a subsequent access without retrieving data from the memory location.