Memory system boot sequence with reduced latency
Methods, systems, and devices for memory system boot sequence are described. A host system may assert a signal (e.g., a fast boot signal) to a pin of a memory system, which may instruct the memory system to communicate data at a first data rate (e.g., a relatively lower data rate) before negotiating to a higher data rate (e.g., a highest data rate). The host system may output the fast boot signal to the memory system based on an estimated size of the data to be transferred, a dynamic measurement of the data, an application associated with the data, or any combination thereof. Based on transferring the data, the host system and the memory system may negotiate to an increased data rate (e.g., up to the highest supported data rate).
1 . A method by a memory system, comprising:
initiating a boot-up sequence to transition the memory system from a first power state to a second power state;
receiving, from a host system based on initiating the boot-up sequence, first signaling to indicate that the boot-up sequence is a first type of sequence associated with lower latency;
communicating first data with the host system according to a first data rate based on receiving the first signaling; and
increasing a rate for communicating with the host system from the first data rate to a second data rate after communicating the first data, wherein the first data rate is slower than the second data rate for communicating with the host system.
2 . The method of claim 1 , further comprising:
communicating second data with the host system according to the second data rate based on increasing the rate for communicating with the host system from the first data rate to the second data rate.
3 . The method of claim 2 , wherein the first data is associated with a first priority level and the second data is associated with a second priority level different from the first priority level.
4 . The method of claim 1 , further comprising:
increasing the rate for communicating with the host system from the second data rate to a third data rate; and
communicating third data with the host system according to the third data rate based on increasing the rate for communicating with the host system from the second data rate to the third data rate, wherein the third data rate is faster than the first data rate and the second data rate for communicating with the host system.
5 . The method of claim 1 , further comprising:
determining that a quantity of the first data satisfies a threshold value based on initiating the boot-up sequence, wherein receiving the first signaling is based on determining that the quantity of the first data satisfies the threshold value.
6 . The method of claim 1 , wherein the memory system is configured to boot-up using a second type of sequence associated with a higher latency than the first type of sequence.
7 . The method of claim 1 , wherein:
the first signaling is received via a first pin of the memory system; and
the first data is communicated with the host system via an interface different from the first pin.
8 . The method of claim 1 , wherein communicating the first data with the host system comprises:
receiving one or more read commands, transmitting one or more write commands, or both.
9 . The method of claim 1 , wherein the first data rate is associated with a slowest data rate for communicating with the host system.
10 . The method of claim 1 , wherein communicating the first data according to the first data rate is based on an application associated with the first data.
11 . A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
initiate a boot-up sequence to transition a memory system from a first power state to a second power state;
receive, from a host system based on initiating the boot-up sequence, first signaling to indicate that the boot-up sequence is a first type of sequence associated with lower latency;
communicate first data with the host system according to a first data rate based on receiving the first signaling; and
increase a rate for communicating with the host system from the first data rate to a second data rate after communicating the first data, wherein the first data rate is slower than the second data rate for communicating with the host system.
12 . The non-transitory computer-readable medium of claim 11 , wherein the instructions are further executable by the one or more processors to:
communicate second data with the host system according to the second data rate based on increasing the rate for communicating with the host system from the first data rate to the second data rate.
13 . The non-transitory computer-readable medium of claim 12 , wherein the first data is associated with a first priority level and the second data is associated with a second priority level different from the first priority level.
14 . The non-transitory computer-readable medium of claim 11 , wherein the instructions are further executable by the one or more processors to:
increase the rate for communicating with the host system from the second data rate to a third data rate; and
communicate third data with the host system according to the third data rate based on increasing the rate for communicating with the host system from the second data rate to the third data rate, wherein the third data rate is faster than the first data rate and the second data rate for communicating with the host system.
15 . The non-transitory computer-readable medium of claim 11 , wherein the instructions are further executable by the one or more processors to:
determine that a quantity of the first data satisfies a threshold value based on initiating the boot-up sequence, wherein receiving the first signaling is based on determining that the quantity of the first data satisfies the threshold value.
16 . The non-transitory computer-readable medium of claim 11 , wherein the memory system is configured to boot-up using a second type of sequence associated with a higher latency than the first type of sequence.
17 . The non-transitory computer-readable medium of claim 11 , wherein:
the first signaling is received via a first pin of the memory system; and
the first data is communicated with the host system via an interface different from the first pin.
18 . The non-transitory computer-readable medium of claim 11 , wherein the instructions to communicate the first data with the host system are executable by the one or more processors to:
receive one or more read commands, transmitting one or more write commands, or both.
19 . The non-transitory computer-readable medium of claim 11 , wherein the first data rate is associated with a slowest data rate for communicating with the host system, or wherein communicating the first data according to the first data rate is based on an application associated with the first data.
20 . A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
initiate a boot-up sequence to transition the memory system from a first power state to a second power state;
receive, from a host system based on initiating the boot-up sequence, first signaling to indicate that the boot-up sequence is a first type of sequence associated with lower latency;
communicate first data with the host system according to a first data rate based on receiving the first signaling; and
increase a rate for communicating with the host system from the first data rate to a second data rate after communicating the first data, wherein the first data rate is slower than the second data rate for communicating with the host system.