IP Library Granted Patent US 12710881
Granted Patent B1
US 12710881 · App. 19/073,648 · Granted Aug 18, 2026

Grown bad block projection of a memory device using fast cycling

Inventors: Yu-Chung Lien (San Jose, CA); Zhenming Zhou (San Jose, CA)
Assignee: Micron Technology, Inc.
G06F3/0614G06F3/064G06F3/0653G06F3/0679
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Quick Facts
Patent No.
US 12710881
App. No.
19/073,648
Granted
Aug 18, 2026
Kind
B1
Abstract

Whether a program erase cycle (PEC) count of a memory device matches a checkpoint value of a set of checkpoint values is determined. First type of cycling of the plurality of blocks of the memory device is performed using a test pattern responsive to determining that the PEC count matches the checkpoint value of the set of checkpoint values. A number of grown bad blocks for the checkpoint value is determined based on the first type of cycling of the plurality of blocks.

Claims (49)

1 . A method comprising:

determining whether a program erase cycle (PEC) count of a memory device matches a checkpoint value of a set of checkpoint values;

responsive to determining that the PEC count matches the checkpoint value of the set of checkpoint values, performing, using a test pattern, a first type of cycling of a plurality of blocks of the memory device; and

determining, based on the first type of cycling of the plurality of blocks, a number of grown bad blocks for the checkpoint value.

2 . The method of claim 1 , wherein each checkpoint value of the set of checkpoint values is a numerical value representing a target PEC count to perform a first type of cycling of the plurality of blocks of the memory device.

3 . The method of claim 1 , wherein performing the first type of cycling of plurality of blocks comprises:

erasing each block of the plurality of blocks;

programming each erased block with the test pattern; and

reading each programmed block.

4 . The method of claim 1 , wherein determining, based on the first type of cycling of the plurality of blocks, the number of grown bad blocks comprises:

for each block of the plurality of blocks experiencing a failure condition in response to the first type of cycling, incrementing the number of grown bad blocks.

5 . The method of claim 4 , wherein the failure condition in response to the first type of cycling includes at least one of an erase failure, a programming failure, or a raw bit error rate exceeding a predetermined threshold.

6 . The method of claim 1 , further comprising:

determining whether the checkpoint value is a largest checkpoint value of the set of checkpoint values; and

responsive to determining that the checkpoint value is not the largest checkpoint value of the set of checkpoint values, performing a second type of cycling of the plurality of blocks, wherein the second type of cycling comprises programming the plurality of blocks with the test pattern and erasing the plurality of blocks.

7 . The method of claim 1 , further comprising:

responsive to determining that the PEC count does not match a checkpoint value of the set of checkpoint values, performing a second type of cycling of the plurality of blocks.

8 . A system comprising:

a memory device; and

a processing device coupled to the memory device, the processing device to perform operations comprising:

determining whether a program erase cycle (PEC) count of the memory device matches a checkpoint value of a set of checkpoint values;

responsive to determining that the PEC count matches the checkpoint value of the set of checkpoint values, performing, using a test pattern, a first type of cycling of a plurality of blocks of the memory device; and

determining, based on the first type of cycling of the plurality of blocks, a number of grown bad blocks for the checkpoint value.

9 . The system of claim 8 , wherein each checkpoint value of the set of checkpoint values is a numerical value representing a target PEC count to perform a first type of cycling of the plurality of blocks of the memory device.

10 . The system of claim 8 , wherein performing the first type of cycling of plurality of blocks comprises:

erasing each block of the plurality of blocks;

programming each erased block with the test pattern; and

reading each programmed block.

11 . The system of claim 8 , wherein determining, based on the first type of cycling of the plurality of blocks, the number of grown bad blocks comprises:

for each block of the plurality of blocks experiencing a failure condition in response to the first type of cycling, incrementing the number of grown bad blocks.

12 . The system of claim 11 , wherein the failure condition in response to the first type of cycling includes at least one of an erase failure, a programming failure, or a raw bit error rate exceeding a predetermined threshold.

13 . The system of claim 8 , wherein the processing device is to perform operations further comprising:

determining whether the checkpoint value is a largest checkpoint value of the set of checkpoint values; and

responsive to determining that the checkpoint value is not the largest checkpoint value of the set of checkpoint values, performing a second type of cycling of the plurality of blocks, wherein the second type of cycling comprises programming the plurality of blocks with the test pattern and erasing the plurality of blocks.

14 . The system of claim 8 , wherein the processing device is to perform operations further comprising:

responsive to determining that the PEC count does not match a checkpoint value of the set of checkpoint values, performing a second type of cycling of the plurality of blocks.

15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

determining whether a program erase cycle (PEC) count of a memory device matches a checkpoint value of a set of checkpoint values;

responsive to determining that the PEC count matches the checkpoint value of the set of checkpoint values, performing, using a test pattern, a first type of cycling of a plurality of blocks of the memory device;

determining, based on the first type of cycling of the plurality of blocks, a number of grown bad blocks for the checkpoint value; and

responsive to determining that the PEC count does not match a checkpoint value of the set of checkpoint values, performing, using the test pattern, a second type of cycling of the plurality of blocks.

16 . The non-transitory computer-readable storage medium of claim 15 , wherein each checkpoint value of the set of checkpoint values is a numerical value representing a target PEC count to perform a first type of cycling of the plurality of blocks of the memory device.

17 . The non-transitory computer-readable storage medium of claim 15 , wherein determining, based on the first type of cycling of the plurality of blocks, the number of grown bad blocks comprises:

for each block of the plurality of blocks experiencing a failure condition in response to the first type of cycling, incrementing the number of grown bad blocks.

18 . The non-transitory computer-readable storage medium of claim 17 , wherein the failure condition in response to the first type of cycling includes at least one of an erase failure, a programming failure, or a raw bit error rate exceeding a predetermined threshold.

19 . The non-transitory computer-readable storage medium of claim 18 , wherein first type of cycling comprises erasing the plurality of blocks, programming the plurality of blocks with the test pattern, and reading the plurality of blocks, and wherein the second type of cycling comprises programming the plurality of blocks with the test pattern, and erasing the plurality of blocks.

20 . The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is to perform operations further comprising:

determining whether the checkpoint value is a largest checkpoint value of the set of checkpoint values; and

responsive to determining that the checkpoint value is not the largest checkpoint value of the set of checkpoint values, performing a second type of cycling of the plurality of blocks, wherein the second type of cycling comprises programming the plurality of blocks with the test pattern and erasing the plurality of blocks.