Program voltage selection during all levels programming of a memory device

1 . A memory device comprising:

a memory array comprising a plurality of memory cells associated with a plurality of pillars and configured as multi-level cell memory; and

control logic, operatively coupled with the memory array, to perform operations comprising:

identifying a set of the plurality of memory cells associated with a selected wordline to be programmed to respective programming levels during a program operation;

causing a set of the plurality of pillars with which the set of the plurality of memory cells are associated to be boosted to respective pillar voltages corresponding to the respective programming levels to enable programming of all of the respective programming levels with each pulse of a series of programming pulses, wherein magnitudes of the respective pillar voltages are inversely proportional to the respective programming levels to which the associated memory cells are being programmed; and

causing the series of programming pulses to be applied to the selected wordline subsequent to the set of the plurality of pillars being boosted to the respective pillar voltages, wherein respective memory cells of the set of memory cells are programmed simultaneously to each of the respective programming levels by each programming pulse in the series of programming pulses, wherein a first programming pulse in the series of programming pulses has a first magnitude and is an initial pulse in the series of programing pulses, wherein a second programming pulse in the series of programming pulses has a second magnitude and is subsequent to the initial pulse in the series of programming pulses, and wherein a difference between the second magnitude of the second programming pulse and the first magnitude of the first programming pulse is less than a predefined pulse step amount.

2 . The memory device of claim 1 , wherein the second magnitude of the second programming pulse is equal to the first magnitude of the first programming pulse.

3 . The memory device of claim 1 , wherein the second magnitude of the second programming pulse is less than the first magnitude of the first programming pulse.

4 . The memory device of claim 1 , wherein a third programming pulse in the series of programming pulses has a third magnitude, and wherein the third magnitude of the third programming pulse is equal to the second magnitude of the second programming pulse increased by the predefined pulse step amount.

5 . The memory device of claim 4 , wherein a fourth programming pulse in the series of programming pulses has a fourth magnitude, and wherein the fourth magnitude of the fourth programming pulse is equal to the third magnitude of the third programming pulse increased by the predefined pulse step amount.

6 . The memory device of claim 1 , wherein the control logic is to perform further operations comprising:

subsequent to each program pulse in the series of programming pulses being applied to the selected wordline, performing a corresponding program verify operation to verify whether the set of the plurality of memory cells were programmed to the respective programming levels.

7 . A method comprising:

identifying a set of memory cells associated with a selected wordline of a memory device to be programmed to respective programming levels during a program operation;

causing a set of pillars with which the set of memory cells are associated to be boosted to respective pillar voltages corresponding to the respective programming levels to enable programming of all of the respective programming levels with each pulse of a series of programming pulses, wherein magnitudes of the respective pillar voltages are inversely proportional to the respective programming levels to which the associated memory cells are being programmed; and

causing the series of programming pulses to be applied to the selected wordline subsequent to the set of pillars being boosted to the respective pillar voltages, wherein respective memory cells of the set of memory cells are programmed simultaneously to each of the respective programming levels by each programming pulse in the series of programming pulses, wherein a first programming pulse in the series of programming pulses has a first magnitude and is an initial pulse in the series of programing pulses, wherein a second programming pulse in the series of programming pulses has a second magnitude and is subsequent to the initial pulse in the series of programming pulses, and wherein a difference between the second magnitude of the second programming pulse and the first magnitude of the first programming pulse is less than a predefined pulse step amount.

8 . The method of claim 7 , wherein the second magnitude of the second programming pulse is equal to the first magnitude of the first programming pulse.

9 . The method of claim 7 , wherein the second magnitude of the second programming pulse is less than the first magnitude of the first programming pulse.

10 . The method of claim 7 , wherein a third programming pulse in the series of programming pulses has a third magnitude, and wherein the third magnitude of the third programming pulse is equal to the second magnitude of the second programming pulse increased by the predefined pulse step amount.

11 . The method of claim 10 , wherein a fourth programming pulse in the series of programming pulses has a fourth magnitude, and wherein the fourth magnitude of the fourth programming pulse is equal to the third magnitude of the third programming pulse increased by the predefined pulse step amount.

12 . The method of claim 7 , further comprising:

subsequent to each program pulse in the series of programming pulses being applied to the selected wordline, performing a corresponding program verify operation to verify whether the set of memory cells were programmed to the respective programming levels.

13 . A memory device comprising:

a memory array comprising a plurality of memory cells associated with a plurality of pillars; and

control logic, operatively coupled with the memory array, to perform operations comprising:

identifying a set of the plurality of memory cells associated with a selected wordline to be programmed to respective programming levels during a program operation;

causing a set of the plurality of pillars with which the set of the plurality of memory cells are associated to be boosted to respective pillar voltages corresponding to the respective programming levels to enable programming of all of the respective programming levels with each pulse of a series of programming pulses, wherein magnitudes of the respective pillar voltages are inversely proportional to the respective programming levels to which the associated memory cells are being programmed; and

causing the series of programming pulses to be applied to the selected wordline subsequent to the set of the plurality of pillars being boosted to the respective pillar voltages, wherein respective memory cells of the set of memory cells are programmed simultaneously to each of the respective programming levels by each programming pulse in the series of programming pulses, wherein a first programming pulse in the series of programming pulses has a first magnitude and is an initial pulse in the series of programing pulses, wherein a second programming pulse in the series of programming pulses has a second magnitude and is subsequent to the initial pulse in the series of programming pulses, and wherein the second magnitude of the second programming pulse is less than the first magnitude of the first programming pulse.

14 . The memory device of claim 13 , wherein a third programming pulse in the series of programming pulses has a third magnitude, and wherein the third magnitude of the third programming pulse is equal to the second magnitude of the second programming pulse increased by a predefined pulse step amount.

15 . The memory device of claim 14 , wherein a fourth programming pulse in the series of programming pulses has a fourth magnitude, and wherein the fourth magnitude of the fourth programming pulse is equal to the third magnitude of the third programming pulse increased by the predefined pulse step amount.

16 . The memory device of claim 13 , wherein the control logic is to perform further operations comprising:

subsequent to each program pulse in the series of programming pulses being applied to the selected wordline, performing a corresponding program verify operation to verify whether the set of the plurality of memory cells were programmed to the respective programming levels.

17 . The memory device of claim 13 , wherein the plurality of memory cells is configured as multi-level cell memory.