IP Library Granted Patent US 12710885
Granted Patent B2
US 12710885 · App. 18/827,461 · Granted Aug 18, 2026

Data relocation based on tracking hard errors in non-volatile memory devices

Inventors: Haobo Wang (San Jose, CA); Fan Zhang (Fremont, CA)
Assignee: SK HYNIX INC.
G06F3/0619G06F3/0653G06F3/0659G06F3/0679G06F11/073G06F11/076G06F11/0793G06F2201/88
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Quick Facts
Patent No.
US 12710885
App. No.
18/827,461
Granted
Aug 18, 2026
Kind
B2
Abstract

Devices, systems, and methods for improving performance of an iterative decoder in a non-volatile memory are described. An example method includes obtaining a hard error percentage, a spare byte percentage, and a total error count associated with a first page in the memory device, determining that the total error count is greater than a threshold value that is determined based on the hard error percentage and the spare byte percentage, and performing, based on the determining, a data relocation operation that relocates at least some data from the first page to a second page different from the first page.

Claims (63)

1 . A method for improving a performance of a memory device, comprising:

obtaining a hard error percentage of a first page in the memory device, a spare byte percentage of the first page, and a total error count associated with the first page,

wherein a hard error in a memory cell of the first page corresponds to a voltage of the memory cell exceeding a range of voltages associated with a soft read of the memory cell,

wherein a spare byte corresponds to an unused byte in the first page, and

wherein the total error count is a total number of bit errors in the first page;

determining that the total error count is greater than a threshold value,

wherein the threshold value is determined based on the hard error percentage and the spare byte percentage; and

performing, based on the determining, a data relocation operation that relocates at least some data from the first page to a second page different from the first page.

2 . The method of claim 1 , wherein the at least some data from the first page comprises all data that can be retrieved from the first page during the data relocation operation.

3 . The method of claim 1 , wherein the data relocation operation is performed during a host read of the first page.

4 . The method of claim 1 , wherein the data relocation operation is performed during a background scan read of the first page.

5 . The method of claim 4 , comprising:

receiving, from a host, a read request for data from the first page; and

routing, subsequent to the data relocation operation, the read request to retrieve the data from the second page.

6 . The method of claim 1 , wherein the memory cell is a single-level cell (SLC) or a multi-level cell (MLC), and the hard error corresponds to the voltage exceeding 400 mV from an optimal read threshold of the memory cell.

7 . The method of claim 1 , wherein the memory cell is a quad-level cell (QLC), and the hard error corresponds to the voltage exceeding 250 mV from an optimal read threshold of the memory cell.

8 . The method of claim 1 , wherein the total error count corresponds to a failed bit count.

9 . The method of claim 1 , wherein the threshold value is determined, based on the hard error percentage (HEP) and the spare byte percentage (SBP), as:

SBP ≤ 8%

8% < SBP ≤ 12%

SBP > 12%

HEP ≤ 10%

500

600

700

10% < HEP ≤ 30%

400

500

500

HEP > 30%

300

400

 300.

10 . A system for improving a performance of a memory device, comprising:

a processor and a memory including instructions stored thereupon, wherein the instructions upon execution by the processor cause the processor to:

obtain a hard error percentage of a first page in the memory device, a spare byte percentage of the first page, and a total error count associated with the first page,

wherein a hard error in a memory cell of the first page corresponds to a voltage of the memory cell exceeding a range of voltages associated with a soft read of the memory cell,

wherein a spare byte corresponds to an unused byte in the first page, and

wherein the total error count is a total number of bit errors in the first page;

determine that the total error count is greater than a threshold value,

wherein the threshold value is determined based on the hard error percentage and the spare byte percentage; and

perform, based on the determining, a data relocation operation that relocates at least some data from the first page to a second page different from the first page.

11 . The system of claim 10 , wherein the at least some data from the first page comprises all data that can be retrieved from the first page during the data relocation operation.

12 . The system of claim 10 , wherein the data relocation operation is performed during a host read of the first page.

13 . The system of claim 10 , wherein the data relocation operation is performed during a background scan read of the first page.

14 . The system of claim 13 , wherein the instructions upon execution by the processor cause the processor to:

receive, from a host, a read request for data from the first page; and

route, subsequent to the data relocation operation, the read request to retrieve the data from the second page.

15 . The system of claim 10 , wherein the total error count corresponds to a failed bit count.

16 . A non-transitory computer-readable storage medium having instructions stored thereupon for improving a performance of a memory device, comprising:

instructions for obtaining a hard error percentage of a first page in the memory device, a spare byte percentage of the first page, and a total error count associated with the first page in the memory device,

wherein a hard error in a memory cell of the first page corresponds to a voltage of the memory cell exceeding a range of voltages associated with a soft read of the memory cell,

wherein a spare byte corresponds to an unused byte in the first page, and

wherein the total error count is a total number of bit errors in the first page;

instructions for determining that the total error count is greater than a threshold value,

wherein the threshold value is determined based on the hard error percentage and the spare byte percentage; and

instructions for performing, based on the determining, a data relocation operation that relocates at least some data from the first page to a second page different from the first page.

17 . The non-transitory computer-readable storage medium of claim 16 , wherein the at least some data from the first page comprises all data that can be retrieved from the first page during the data relocation operation.

18 . The non-transitory computer-readable storage medium of claim 16 , wherein the data relocation operation is performed during a host read of the first page.

19 . The non-transitory computer-readable storage medium of claim 16 , wherein the data relocation operation is performed during a background scan read of the first page.

20 . The non-transitory computer-readable storage medium of claim 19 , comprising:

receiving, from a host, a read request for data from the first page; and

routing, subsequent to the data relocation operation, the read request to retrieve the data from the second page.