Reclaim unit organization by endurance capability
Aspects of the present disclosure configure a memory sub-system controller to allow a host to control storage on the memory sub-system based on endurance of memory components. The controller groups the set of memory components into a plurality of categories representing different endurance levels of the set of memory components and communicates, to a host, information about the plurality of categories. The controller receives, from the host, a request to program data into an individual memory component of the set of memory components, the request being generated by the host based on a type of the data and an individual category associated with the individual memory component.
1 . A system comprising:
a set of memory components of a memory sub-system; and
at least one processing device operatively coupled to the set of memory components, the at least one processing device being configured to perform operations comprising:
receiving configuration data, from a host, indicating a maximum quantity of program-erase (PE) cycles that can be performed for different groups of memory components of the set of memory components;
based on the configuration data that has been previously received, grouping the set of memory components into a plurality of categories comprising at least three categories including a high endurance category, a medium endurance category, and a low endurance category representing different endurance levels of the set of memory components comprising the maximum quantity of PE cycles that can be performed, the maximum quantity of PE cycles being tracked separately from current PE cycles associated with each memory component of the set of memory components, wherein the high endurance category corresponds to memory components having a maximum quantity of PE cycles above a first threshold, the medium endurance category corresponds to memory components having a maximum quantity of PE cycles between the first threshold and a second threshold, and the low endurance category corresponds to memory components having a maximum quantity of PE cycles below the second threshold, and wherein a first block of an individual memory component of the set of memory components is associated with a first category comprising the high endurance category representing a maximum quantity of PE cycles above the first threshold and a second block of the individual memory component is associated with a second category comprising the medium endurance category maximum quantity of PE cycles between the first threshold and the second threshold;
communicating, to the host, information identifying the at least three categories; and
receiving, from the host, a request to program data into an individual memory component of the set of memory components, the request being generated by the host based on a type of the data and the information identifying the at least three categories.
2 . The system of claim 1 , wherein the memory sub-system includes Flexible Data Placement (FDP).
3 . The system of claim 2 , the operations comprising:
grouping the set of memory components into a plurality of reclaim groups (RGs), each RG of the plurality of RGs comprising a subset of reclaim units (RUS).
4 . The system of claim 3 , wherein information, communicated to the host, indicates which of the plurality of categories is associated with each RU.
5 . The system of claim 4 , wherein the information indicates which of the plurality of categories is associated with each RG.
6 . The system of claim 3 , the operations comprising:
folding data in a first RG of the plurality of RGs using the subset of RUs of the first RG without folding the data into any RU of another RG of the plurality of RGs to keep the data stored in the first RG.
7 . The system of claim 3 , wherein garbage collection operations performed on an individual RU of a first RG of the plurality of RGs fold data using only RUs of the first RG without folding data into any RU of another RG of the plurality of RGs.
8 . The system of claim 3 , wherein the plurality of categories represents respective organization of storage blocks by bits per cell, the operations comprising receiving the configuration data from the host, and wherein the organization by bits per cell includes single level cell (SLC) organization, triple level cell (TLC) organization, and quad level cell (QLC) organization.
9 . The system of claim 1 , the operations comprising:
determining, by the host, that the type of data corresponds to data that is overwritten less than a threshold quantity of times; and
in response to determining that the type of data corresponds to data that is overwritten less than the threshold quantity of times, selecting, by the host, the individual category corresponding to a first endurance level that is lower than a second endurance level.
10 . The system of claim 9 , the operations comprising:
generating the request to program the data using a write handle associated with the individual category corresponding to the first endurance level.
11 . The system of claim 1 , the operations comprising:
determining, by the host, that the type of data corresponds to data that is overwritten greater than a threshold quantity of times; and
in response to determining that the type of data corresponds to data that is overwritten greater than the threshold quantity of times, selecting, by the host, the individual category corresponding to a first endurance level that is greater than a second endurance level.
12 . The system of claim 1 , the operations comprising:
determining, by the host, that the type of data corresponds to data that is overwritten greater than a threshold quantity of times, the data correspond to random host writes; and
in response to determining that the type of data corresponds to data that is overwritten greater than the threshold quantity of times, selecting, by the host, the individual category corresponding to a first bit level organization that is less dense than a second bit level organization.
13 . The system of claim 12 , wherein the first bit level organization corresponds to single level cell (SLC) storage, and wherein the second bit level organization corresponds to tri level cell (TLC) storage or quad level cell (QLC) storage.
14 . The system of claim 1 , the operations comprising:
storing a table that maps the different groups of the set of memory components to respective endurance levels comprising lifetime PE cycle (PEC) values and current PEC values.
15 . The system of claim 1 , the operations comprising:
grouping the set of memory components into a plurality of reclaim groups (RGs), each RG of the plurality of RGs comprising a subset of reclaim units (RUS), a first of the RUs of an individual one of the plurality of RGs being associated with the first category, and a second of the RUs of the individual one of the plurality of RGs being associated with the second category.
16 . The system of claim 15 , the operations comprising:
generating an instruction by the host to program the data using an RU handle associated with the second of the RUs.
17 . A method comprising:
receiving configuration data, from a host, indicating a maximum quantity of program-erase (PE) cycles that can be performed for different groups of memory components of a set of memory components;
based on the configuration data that has been previously received, grouping the set of memory components into a plurality of categories comprising at least three categories including a high endurance category, a medium endurance category, and a low endurance category representing different endurance levels of the set of memory components comprising the maximum quantity of PE cycles that can be performed, the maximum quantity of PE cycles being tracked separately from current PE cycles associated with each memory component of the set of memory components, wherein the high endurance category corresponds to memory components having a maximum quantity of PE cycles above a first threshold, the medium endurance category corresponds to memory components having a maximum quantity of PE cycles between the first threshold and a second threshold, and the low endurance category corresponds to memory components having a maximum quantity of PE cycles below the second threshold, and wherein a first block of an individual memory component of the set of memory components is associated with a first category comprising the high endurance category representing a maximum quantity of PE cycles above the first threshold and a second block of the individual memory component is associated with a second category comprising the medium endurance category maximum quantity of PE cycles between the first threshold and the second threshold;
communicating, to the host, information identifying the at least three categories; and
receiving, from the host, a request to program data into an individual memory component of the set of memory components, the request being generated by the host based on a type of the data and the information identifying the at least three categories.
18 . A non-transitory computer-readable storage medium comprising instructions that, when executed by at least one processing device, cause the at least one processing device to perform operations comprising:
receiving configuration data, from a host, indicating a maximum quantity of program-erase (PE) cycles that can be performed for different groups of memory components of a set of memory components;
based on the configuration data that has been previously received, grouping the set of memory components into a plurality of categories comprising at least three categories including a high endurance category, a medium endurance category, and a low endurance category representing different endurance levels of the set of memory components comprising the maximum quantity of PE cycles that can be performed, the maximum quantity of PE cycles being tracked separately from current PE cycles associated with each memory component of the set of memory components, wherein the high endurance category corresponds to memory components having a maximum quantity of PE cycles above a first threshold, the medium endurance category corresponds to memory components having a maximum quantity of PE cycles between the first threshold and a second threshold, and the low endurance category corresponds to memory components having a maximum quantity of PE cycles below the second threshold, and wherein a first block of an individual memory component of the set of memory components is associated with a first category comprising the high endurance category representing a maximum quantity of PE cycles above the first threshold and a second block of the individual memory component is associated with a second category comprising the medium endurance category maximum quantity of PE cycles between the first threshold and the second threshold;
communicating, to the host, information identifying the at least three categories; and
receiving, from the host, a request to program data into an individual memory component of the set of memory components, the request being generated by the host based on a type of the data and the information identifying the at least three categories.
19 . The non-transitory computer-readable storage medium of claim 18 ,
wherein the host determines that the type of data corresponds to ephemeral data that is not retained for more than a threshold period, and in response to determining that the type of data corresponds to ephemeral data, the host selects the low endurance category.
20 . The non-transitory computer-readable storage medium of claim 18 , wherein memory components grouped into a same category of the at least three categories are wear leveled as a pool to spread program-erase cycles across the memory components in the pool.