Tensor non-linear signal processing random access memory

1 . A system comprising:

a first circuit configured to receive tensorized input data associated with a plasma power generator; and

a second circuit configured to generate a tensor output, wherein the output of the first circuit is operably coupled to one or more inputs of the second circuit wherein the tensorized input data and the tensor output have a same number of dimensions; and

a controller configured to receive the tensor output and to produce, responsive to the tensor output, a signal to control the plasma power generator, wherein the tensorized input data comprises, one of, a fast tensor, a slow tensor, and frequency tensor, and wherein the tensor output comprises, at least one of, a corresponding fast control tensor, a corresponding slow control tensor, and a corresponding frequency tuning control tensor.

2 . The system of claim 1 , wherein when the system detects a state input having a state for a first time, the system is configured to store the tensor output for retrieval a next time that the system detects the state input having the state.

3 . The system of claim 1 , wherein the first circuit comprises a volatile memory circuit for performing multi-dimensional digital signal processing in a plurality of dimensions, wherein the plurality of dimensions corresponds to a number of dimensions of the tensorized input data and a number of dimensions of the tensor output.

4 . The system of claim 2 , wherein the second circuit is configured to:

receive one or more full data in inputs;

receive one or more full write enable inputs;

receive one or more write and/or read addresses;

output one or more data out outputs; and

output one or more data out valid outputs.

5 . The system of claim 4 , wherein the second circuit further comprises:

a volatile memory tensor adaptor circuit; and

a select by index circuit,

wherein the volatile memory tensor adaptor circuit comprises the volatile memory circuit, and is configured to output one or more read out outputs to the select by index circuit, and

wherein the select by index circuit is configured to: receive the one or more read out outputs from the volatile memory processing circuit;

receive one or more read address inputs; and

output the one or more data out outputs.

6 . The system of claim 1 , wherein the first circuit comprises:

a select tensor write enable and data in algorithm processing circuit, wherein the output of the select tensor write enable and data in algorithm processing circuit is operably coupled to an input of the second circuit.

7 . The system of claim 6 , wherein the select tensor write enable and data in algorithm processing circuit is configured to: pass an initialization data set when a new state is encountered.

8 . The system of claim 6 , wherein the first circuit further comprises:

a tensor write enable and data in formation algorithm processing circuit, wherein an output of the tensor write enable circuit and data in formation algorithm processing circuit is operably coupled to an input of the select tensor write enable and data in algorithm processing circuit.

9 . The system of claim 8 , wherein the tensor write enable and data in formation algorithm processing circuit is configured to: receive a write enable input;

perform n-dimensional tensor assignment to the write enable input, thereby generating an n-dimensional write enable tensor output based at least in part on the write enable input; and

output the n-dimensional write enable tensor output.

10 . The system of claim 8 , wherein the tensor write enable and data in formation algorithm processing circuit is configured to: receive a data in input;

perform n-dimensional tensor assignment to the data in input, thereby generating an n-dimensional data in tensor output based at least in part on the data in input; and

output the n-dimensional data in tensor output.

11 . The system of claim 6 , wherein the first circuit further comprises:

an edge enable algorithm processing circuit, wherein an output of the edge enable algorithm processing circuit is operably coupled to an input of the select tensor write enable and data in algorithm processing circuit.

12 . The system of claim 1 , wherein the first circuit comprises:

a data in input;

a data in valid input;

a write address input;

a write enable input;

a read address input; and a read enable input, and

wherein the second circuit comprises: a data out output; and

a data out valid output.

13 . The system of claim 1 , wherein the first circuit is a first tensor data pre-processing circuit, and the second circuit is a first tensor data write/read circuit,

the system further comprising:

a plurality of tensor processing blocks, wherein the plurality of tensor processing blocks comprises a first tensor processing block, wherein the first tensor processing block comprises the first tensor data pre-processing circuit and the first tensor data write/read circuit,

wherein each respective tensor processing block of the plurality of tensor processing blocks comprises a respective tensor data pre-processing circuit and a respective tensor data write/read circuit.

14 . A method comprising:

pre-processing, by a first circuit of a volatile memory system, tensor data associated with a power generator, the tensorized input data comprising, at least one of, a fast tensor, a slow tensor, and frequency tensor;

communicating, by the first circuit, the pre-processed tensor data to a second circuit of the volatile memory system comprising, at least one of, a corresponding fast tensor, a corresponding slow tensor, and a corresponding frequency tensor;

processing, by the second circuit, the pre-processed tensor data;

outputting, by the second circuit, processed tensor data; and

controlling the power generator based on the processed tensor data.

15 . The method of claim 14 , wherein the second circuit comprises a volatile memory circuit, wherein processing the pre-processed tensor data comprises:

decomposing, by the second circuit, the pre-processed tensor data to one-dimensional data;

processing, by the volatile memory circuit, the one-dimensional data; and

generating, by the second circuit, the processed tensor data, based at least in part on the processed one-dimensional data; and

wherein the pre-processed tensor data and the processed tensor data have a same number of dimensions.

16 . The method of claim 14 , further comprising:

detecting a state input having a state for a first time;

storing the processed tensor data and associating it with the state; and

when again detecting the state input having the state, accessing the processed tensor data.

17 . The method of claim 16 , further comprising controlling the power generator a second time after again detecting the state input having the state, based on accessing the processed tensor data.

18 . An integrated circuit comprising:

a first circuit configured to receive tensorized input data associated with a plasma power generator, the tensorized input data comprising, at least one of, a fast tensor, a rail slow tensor, and frequency tensor; and

a second circuit configured to generate a tensor output comprising, at least one of, a corresponding fast tensor, a corresponding rail slow tensor, and a corresponding frequency tensor,

wherein an output of the first circuit is operably coupled to an input of the second circuit.

19 . The integrated circuit of claim 18 , wherein when the integrated circuit detects a state input having a state for a first time, the integrated circuit is configured to store the tensor output for retrieval a next time that the integrated circuit detects the state input having the state.

20 . The integrated circuit of claim 18 , wherein the first circuit is configured by the first set of instructions to: pass an initialization data set when a new state is encountered.

21 . The integrated circuit of claim 18 , wherein the first circuit comprises:

a select tensor write enable and data in algorithm processing circuit, wherein an output of the select tensor write enable and data in algorithm processing circuit is operably coupled to an input of the second circuit.