Address verification at a memory system
Methods, systems, and devices for address verification at a memory system are described. A memory system may determine an address identifier based on a received read command and maintain the determined address identifier in a protected state to validate a subsequent read operation. For example, the memory system may store the determined address identifier in a first memory array, separate from a second memory array that is read from in response to the read command. The memory system may also extract an address identifier from memory cells being read in response to the read command, which may include decoding or other interpreting operations performed on information read from the memory cells. The address identifier extracted from the memory cells may be compared with the address identifier determined from the read command and maintained in the protected state, which may support a determination of how to respond to the read command.
1 . A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive a command to read data from the memory system, the command comprising a first address identifier associated with the data;
perform an error control operation on the first address identifier based at least in part on the command;
store, to a first memory array, an indication of the first address identifier with parity information associated with the error control operation;
read the data and an indication of a second address identifier from a second memory array of the one or more memory devices based at least in part on the command; and
respond to the command based at least in part on a comparison of the second address identifier with the first address identifier after storing the first address identifier with the parity information.
2 . The memory system of claim 1 , wherein the processing circuitry is further configured to:
determine the first address identifier in accordance with a command universal protocol information unit of the command.
3 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
perform the error control operation on a transfer length associated with the command, a task tag associated with the command, or both; and
store an indication of the transfer length, an indication of the task tag, or both to the first memory array, wherein responding to the command is based at least in part on storing the indication of the transfer length, the indication of the task tag, or both.
4 . The memory system of claim 1 , wherein the parity information comprises single error correction double error detection information associated with the first address identifier.
5 . The memory system of claim 1 , wherein the parity information comprises a plurality of parity bits appended to the indication of the first address identifier.
6 . The memory system of claim 1 , wherein the first memory array is associated with a different storage location than the second memory array.
7 . The memory system of claim 6 , wherein the first memory array is included in one or more controllers of the processing circuitry.
8 . The memory system of claim 6 , wherein the first memory array comprises one or more registers of the memory system.
9 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to:
receive a command to read data from the electronic device, the command comprising a first address identifier associated with the data;
perform an error control operation on the first address identifier based at least in part on the command;
store, to a first memory array, an indication of the first address identifier with parity information associated with the error control operation;
read the data and an indication of a second address identifier from a second memory array of the electronic device based at least in part on the command; and
respond to the command based at least in part on a comparison of the second address identifier with the first address identifier after storing the first address identifier with the parity information.
10 . The non-transitory computer-readable medium of claim 9 , wherein the instructions, when executed by the processing circuitry of the electronic device, cause the electronic device to:
determine the first address identifier in accordance with a command universal protocol information unit of the command.
11 . The non-transitory computer-readable medium of claim 9 , wherein the instructions, when executed by the processing circuitry of the electronic device, cause the electronic device to:
perform the error control operation on a transfer length associated with the command, a task tag associated with the command, or both; and
store an indication of the transfer length, an indication of the task tag, or both to the first memory array, wherein responding to the command is based at least in part on storing the indication of the transfer length, the indication of the task tag, or both.
12 . The non-transitory computer-readable medium of claim 9 , wherein the parity information comprises single error correction double error detection information associated with the first address identifier.
13 . The non-transitory computer-readable medium of claim 9 , wherein the parity information comprises a plurality of parity bits appended to the indication of the first address identifier.
14 . The non-transitory computer-readable medium of claim 9 , wherein the first memory array is associated with a different storage location than the second memory array.
15 . The non-transitory computer-readable medium of claim 14 , wherein the first memory array is included in one or more controllers of the processing circuitry.
16 . The non-transitory computer-readable medium of claim 14 , wherein the first memory array comprises one or more registers of a memory system.