Separate command address (SCA) based memory controller

1 . A method, comprising:

receiving, by a separate command address (SCA)-based memory controller, a plurality of commands,

wherein the received plurality of commands includes high-level commands that are translated to observe an SCA protocol; and

wherein a particular SCA-based command under the SCA protocol includes a select chip enable (SCE) field and a select chip terminate (SCT) field;

scheduling, by the SCA-based memory controller, the plurality of commands using two or more data path scheduler (DPS) request queues;

converting the scheduled commands into SCA-based commands;

selecting, from the scheduled SCA-based commands, one or more scheduled SCA-based commands for a sequence execution; and

executing, in sequence, the selected one or more SCA-based commands using one or more logical units (LUNs) of a channel in a memory component.

2 . The method of claim 1 , wherein the scheduling of the plurality of commands further comprises:

scheduling a first command that is associated with a first operation using a first DPS request queue; and

scheduling, in parallel, a second command that is associated with a second operation using a second DPS request queue, wherein the first operation is independent from the second operation.

3 . The method of claim 1 , wherein the scheduling of the plurality of commands further comprises:

tracking a DPS request queue that is associated with a processing of a first command; and

scheduling a second command in the tracked DPS request queue, wherein the second command is associated with an operation that is dependent upon an operation of the first command.

4 . The method of claim 3 , further comprising: using a look-up table (LUT) to track the operations between the first command and the second command.

5 . The method of claim 1 , further comprising: executing in sequence the selected one or more scheduled SCA-based commands via a plurality of NAND flash controller (NFC) queues.

6 . The method of claim 1 further comprising: sending notification to a DPS, wherein the notification includes status of execution in the one or more LUNs.

7 . The method of claim 1 , wherein the memory component includes a NAND flash memory.

8 . The method of claim 1 , wherein the SCE field and the SCT field are used as references for an associated data transfer in a data bus.

9 . An apparatus, comprising:

a memory component; and

a separate command address (SCA)-based memory controller coupled to the memory component and configured to:

receive a plurality of commands,

wherein the received plurality of commands includes high-level commands that are translated to observe an SCA protocol; and

wherein a particular SCA-based command under the SCA protocol includes a select chip enable (SCE) field and a select chip terminate (SCT) field;

schedule the plurality of commands using two or more data path scheduler (DPS) request queues;

convert the scheduled plurality of commands into SCA-based commands;

select from the scheduled SCA-based commands one or more scheduled SCA-based commands for a sequence execution; and

execute in sequence the selected one or more SCA-based commands using one or more logical units (LUNs) of a channel in the memory component.

10 . The apparatus of claim 9 , wherein the SCA-based memory controller is further configured to:

schedule in parallel the commands using corresponding DPS request queues, wherein the commands are associated with operations that are independent from one another.

11 . The apparatus of claim 9 , wherein the SCA-based memory controller is further configured to:

identify different fields on each of the scheduled SCA-based commands; and

use the identified different fields to implement overlapping between the SCA-based commands.

12 . The apparatus of claim 11 , wherein the identified different fields include a Select Chip Enable (SCE) field and a Select Chip Terminate (SCT) field.

13 . The apparatus of claim 12 , wherein the SCE field and the SCT field are used as references for an associated data burst in a data (DQ) bus.

14 . The apparatus of claim 9 , wherein the SCA-based memory controller is further configured to:

use a look-up table (LUT) to track status of scheduled commands; and

use the tracked status to schedule a next command.

15 . The apparatus of claim 9 , wherein the SCA-based memory controller is further configured to:

generate a sequence of command executions for an ONFI-based memory component.

16 . An apparatus, comprising:

a storage device comprising:

a memory component; and

a memory controller that is further configured to:

receive a plurality of commands,

wherein the received plurality of commands includes high-level commands that are translated to observe an SCA protocol; and

wherein a particular SCA-based command under the SCA protocol includes a select chip enable (SCE) field and a select chip terminate (SCT) field;

schedule the plurality of commands using two or more data path scheduler (DPS) request queues;

select from the scheduled commands one or more scheduled commands for a sequence execution; and

execute in sequence the selected one or more using one or more logical units (LUNs) of a channel in the memory component.

17 . The apparatus of claim 16 , wherein the memory controller selects the one or more scheduled commands for the sequence execution based on a request priority associated with each of the scheduled commands.

18 . The apparatus of claim 16 , wherein the memory controller selects the one or more scheduled commands for the sequence execution based on a workload in the one or more LUNs.