Programmable device implementing fixed and floating point functionality in a mixed architecture

1 . An integrated circuit device comprising a first processing block, wherein the first processing block comprises:

one or more inputs;

one or more outputs; and

a common processing pipeline comprising:

a first multiplication stage configurable to generate one or more intermediate vectors during a first clock cycle;

one or more registers configurable to collectively store the one or more intermediate vectors;

a second multiplication stage configurable to receive the one or more intermediate vectors from the one or more registers and generate one or more final vectors during a subsequent clock cycle, wherein each of the one or more final vectors is based on all of the one or more intermediate vectors stored by the one or more registers, and wherein the first multiplication stage and the second multiplication stage are configurable to:

implement fixed-point multiplication operations via the common processing pipeline; and

implement floating-point multiplication operations via the common processing pipeline.

2 . The integrated circuit device of claim 1 , wherein the first processing block comprises a digital signal processor (DSP).

3 . The integrated circuit device of claim 1 , wherein the common processing pipeline comprises an arithmetic logic unit configurable to implement floating-point addition or subtraction operations.

4 . The integrated circuit device of claim 1 , comprising memory, wherein the one or more inputs are configured to receive one or more values from the memory.

5 . The integrated circuit device of claim 1 , wherein the circuitry is configurable to perform multiply-accumulate operations.

6 . The integrated circuit device of claim 5 , comprising one or more additional registers configurable to store one or more values, wherein the circuitry is configurable to:

pre-load a value of the one or more values for accumulation with a product generated by a multiplication operation; and

perform a zeroing function by disabling accumulation.

7 . The integrated circuit device of claim 5 , wherein the floating-point multiplication operations or the multiply-accumulate operations comprise one or more operations involving one or more floating-point values having thirty-two bits.

8 . The integrated circuit device of claim 7 , wherein the fixed-point multiplication operations or the multiply-accumulate operations comprise one or more operations involving one or more integer values having fewer than eighteen bits.

9 . The integrated circuit device of claim 1 , wherein the fixed-point multiplication operations and the floating-point multiplication operations propagate from the first multiplication stage to the second multiplication stage through each of the one or more registers.

10 . The integrated circuit device of claim 1 , wherein the first processing block is a first processing block of a plurality of processing blocks, and wherein a second processing block of the plurality of processing blocks comprises:

one or more second inputs;

one or more second outputs;

a second common processing pipeline comprising:

a third multiplication stage configurable to generate one or more second intermediate vectors during the first clock cycle;

one or more second registers configurable to collectively store the one or more second intermediate vectors;

a fourth multiplication stage configurable to receive the one or more second intermediate vectors from the one or more second registers and generate one or more second final vectors during the subsequent clock cycle, wherein each of the one or more second final vectors is based on all of the one or more second intermediate vectors stored by the one or more second registers, and wherein the third multiplication stage and the fourth multiplication stage are configurable to:

implement the fixed-point multiplication operations via the second common processing pipeline; and

implement the floating-point multiplication operations via the second common processing pipeline.

11 . A processing block implemented on an integrated circuit device, wherein the processing block comprises:

one or more inputs;

one or more outputs; and

a common processing pipeline comprising:

a first multiplication stage configurable to generate one or more intermediate vectors during a first clock cycle;

one or more registers configurable to collectively store the one or more intermediate vectors;

a second multiplication stage configurable to receive the one or more intermediate vectors from the one or more registers and generate one or more final vectors during a subsequent clock cycle, wherein each of the one or more final vectors is based on all of the one or more intermediate vectors stored by the one or more registers, and wherein the first multiplication stage and the second multiplication stage are configurable to:

implement fixed-point multiplication operations on fixed-point values via the common processing pipeline; and

implement floating-point multiplication operations on single-precision floating-point values via the common processing pipeline.

12 . The processing block of claim 11 , wherein the circuitry is configurable to implement floating-point addition and multiply-accumulate operations, and vector dot product operations.

13 . The processing block of claim 12 , wherein the multiply-accumulate operations comprise one or more operations involving floating-point values having twenty-three mantissa bits.

14 . The processing block of claim 13 , wherein the circuitry is configurable to implement fixed-point addition involving the fixed-point values.

15 . The processing block of claim 14 , wherein the fixed-point values comprise eight-bit integers.

16 . The processing block of claim 14 , wherein an output value of performing the floating-point multiplication operations comprises a floating-point value having thirty-two bits.

17 . A system comprising:

memory; and

a processing block comprising:

one or more inputs configurable to receive one or more values from the memory;

one or more outputs; and

a common processing pipeline comprising:

a first multiplication stage configurable to generate one or more intermediate vectors during a first clock cycle;

one or more registers configurable to collectively store the one or more intermediate vectors;

a second multiplication stage configurable to receive the one or more intermediate vectors from the one or more registers and generate one or more final vectors during a subsequent clock cycle, wherein each of the one or more final vectors is based on all of the one or more intermediate vectors stored by the one or more registers, and wherein the first multiplication stage and the second multiplication stage are configurable to:

implement fixed-point multiplication operations and fixed-point addition operations on fixed-point values via the common processing pipeline; and

implement floating-point multiplication operations, floating-point addition operations, and floating-point multiply-accumulate operations on floating-point values via the common processing pipeline.

18 . The system of claim 17 , wherein the common processing pipeline comprises an arithmetic logic unit configurable to perform floating-point addition or subtraction operations.

19 . The system of claim 18 , wherein:

the fixed-point values comprise eight-bit integers or sixteen-bit integers; and

the floating-point values comprise single-precision floating-point values.

20 . The system of claim 18 , wherein the memory comprises random-access memory (RAM).