System and method for efficient even polynomial evaluation using transformation-enhanced fused multiply-add operations
A hardware processing system for evaluating degree-2n even polynomials comprises a plurality of fused multiply-add (FMA) units fabricated on a semiconductor substrate, each having dedicated multiplication circuitry and addition circuitry operating in parallel. A scheduling controller with dependency analysis circuitry orchestrates polynomial evaluation by allocating FMA units and configuring hardware interconnect circuitry comprising signal paths, multiplexers, and routing logic. A configuration memory stores pre-computed transformation constants and restructured polynomial coefficients as fixed hardware parameters. The system modifies conventional processor datapath architecture by routing the transformation constant from configuration memory to the addition input of a first FMA unit during squaring operations, productively utilizing addition circuitry that would conventionally receive hardwired zero values. The transformation constant restructures computational dependencies, enabling the scheduling controller to dispatch parallel FMA operations to separate units during the same clock cycle.
1 . A hardware processing system comprising:
a plurality of floating-point multiply-add (FMA) units each configured with dedicated multiplication circuitry and addition circuitry operating in parallel within each FMA unit;
a scheduling controller configured for instructing a degree-2n polynomial evaluation completed using no more than n FMA operations by:
acquiring a transformation constant (α) and a plurality of restructured polynomial coefficients optimized for FMA operations,
configuring a first FMA unit from the plurality of FMA units to compute an intermediate processing variable (y) by exploiting both the multiplication capability and the addition capability of the FMA unit simultaneously, wherein the transformation constant (α) is added during computation of the intermediate processing variable (y=x 2 +α) where x is an input value of the first FMA, and
allocating one or more additional FMA units from the plurality of FMA units to execute FMA operations using the intermediate processing variable,
wherein the transformation constant (α) restructures computational dependencies to enable calculation of intermediate polynomial terms by the one or more additional FMA units using the plurality of restructured polynomial coefficients.
2 . The hardware processing system of claim 1 , wherein the FMA operations compute a round ((a×b)+c) operation in a single operation with a single rounding where a, b, and c are operands.
3 . The hardware processing system of claim 1 , wherein the one or more additional FMA units using independent inputs during a same clock cycle.
4 . The hardware processing system of claim 1 , wherein configuring the first FMA unit to compute the intermediate processing variable comprises computing fma(x, x, α) where α is the transformation constant.
5 . The hardware processing system of claim 4 , wherein the transformation constant α is determined by solving a third-degree polynomial equation derived from a coefficient relationship condition, where the product of a first transformed coefficient and a second transformed coefficient equals the product of a third transformed coefficient and a fourth transformed coefficient.
6 . The hardware processing system of claim 1 , wherein the degree-2n even polynomial represents an approximation of a trigonometric function selected from the group consisting of cosine functions and normalized sine functions.
7 . The hardware processing system of claim 1 , wherein the configuration memory stores a plurality of sets, each set comprising, corresponding to a different function, the following: (1) one of a plurality of transformation constants and (2) one of a plurality of groups each having a plurality of restructured polynomial coefficients, and wherein the scheduling controller selects among the plurality of sets based on a function identifier associated with a current computational workload.
8 . The hardware processing system of claim 7 , wherein each set is computed during a compilation phase or hardware configuration phase and remains fixed during runtime polynomial evaluation operations.
9 . The hardware processing system of claim 1 , wherein the one or more additional FMA units are allocated by computing a fifth-degree polynomial segment using four FMA operations, wherein the four FMA operations include at least two FMA operations that execute in parallel using independent inputs, and wherein a coefficient relationship condition specifies that the product of a second-degree coefficient and a fifth-degree coefficient equals the product of a third-degree coefficient and a fourth-degree coefficient.
10 . The hardware processing system of claim 9 , wherein computing the fifth-degree polynomial segment using four FMA operations comprises: computing a first intermediate result by multiplying an input value by itself and adding a first pre-computed offset based on the plurality of reconstructed polynomial coefficients; computing a second intermediate result by multiplying a first coefficient by the input value and adding a second coefficient, wherein the first intermediate result and the second intermediate result are computed in parallel during a same clock cycle; computing a third intermediate result by multiplying the first intermediate result by itself and adding a third pre-computed offset based on the plurality of reconstructed polynomial coefficients; and computing a fourth intermediate result by multiplying the third intermediate result by the second intermediate result and adding a fourth pre-computed offset based on the plurality of reconstructed polynomial coefficients.
11 . The hardware processing system of claim 1 , wherein the degree-2n even polynomial has degree twelve, and wherein the parallel FMA operations compute the polynomial using exactly six FMA operations.
12 . The hardware processing system of claim 1 , further comprising a compiler configured to analyze function requirements and generate the restructured polynomial coefficients by determining the transformation constant that satisfies relationships of the plurality of reconstructed polynomial coefficients.
13 . The hardware processing system of claim 2 , wherein each FMA unit performs multiplication and addition with a single rounding operation according to IEEE 754-2008 standard.
14 . The hardware processing system of claim 1 , wherein the transformation constant is stored in the configuration memory as a fixed hardware parameter determined during a hardware configuration phase prior to runtime operation, and wherein the scheduling controller retrieves the transformation constant from the configuration memory and routes it to an addition input of the first FMA unit.
15 . The hardware processing system of claim 1 , further comprising hardware interconnect circuitry connecting outputs of the first FMA unit to inputs of subsequent FMA units, wherein the scheduling controller configures the hardware interconnect circuitry to enable at least two of the subsequent FMA units to receive input data in parallel during a single clock cycle.
16 . The hardware processing system of claim 1 , wherein the plurality of FMA units are implemented as dedicated floating-point arithmetic circuits on a semiconductor substrate.
17 . The hardware processing system of claim 1 , wherein the one or more additional FMA units execute the FMA operations using the intermediate processing variable simultaneously.
18 . A computer-implemented method for evaluating even polynomials in a hardware computing system, comprising:
performing a degree-2n even polynomial evaluation completed using no more than n FMA operations by:
acquiring, by a scheduling controller from a configuration memory, a transformation constant (α) and a plurality of restructured polynomial coefficients optimized for floating-point multiply-add (FMA) operations;
receiving an input value at a first FMA unit from a plurality of FMA units, the first FMA unit having dedicated multiplication circuitry and addition circuitry;
configuring the first FMA unit to compute an intermediate processing variable (y) by executing a multiply-add operation that utilizes both the multiplication circuitry and the addition circuitry in a single hardware operation, wherein the transformation constant (α) is added during computation of the intermediate processing variable (y=x 2 +α) where x is an input value of the first FMA;
allocating, by the scheduling controller, at least two additional FMA units from the plurality of FMA units to execute parallel FMA operations using the intermediate processing variable and independent inputs to generate intermediate polynomial terms, wherein the transformation constant (α) restructures computational dependencies to enable parallel calculation of the intermediate polynomial terms; and
performing additional FMA operations through the plurality of FMA units to process the intermediate polynomial terms using the plurality of restructured polynomial coefficients and complete the polynomial evaluation.
19 . The method of claim 18 , wherein determining the transformation constant comprises optimizing the transformation constant to satisfy a condition that restructures the polynomial to enable efficient evaluation using reduced FMA operations.