IP Library Granted Patent US 12,710,943
Granted Patent B2
US 12,710,943 · App. 17/934,584 · Granted Aug 18, 2026

Method for managing a runtime system for a hybrid computing architecture, managed runtime system, apparatus and computer program

Inventor: Mingqiu Sun (Beaverton, OR)
Assignee: Intel Corporation
G06F8/447G06F8/31G06F8/451G06F9/4881G06F9/5066
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Quick Facts
Patent No.
US 12,710,943
App. No.
17/934,584
Granted
Aug 18, 2026
Kind
B2
Abstract

Examples relate to a method for managing a runtime system for a hybrid computing architecture, a device, an apparatus and to a corresponding computer program. The apparatus is configured to create a thread pool for each work thread of a computer program, generate native code for at least one of the at least two ISAs for code segments of the computer program, assign native code sequences to a corresponding thread in the thread pool for execution, with the native code sequences comprising the native code of the code segments, and execute the native code sequences.

Claims (39)

1 . A managing apparatus for a hybrid architecture containing cores with at least two different Instruction Set Architectures (ISAs), the managing apparatus comprising interface circuitry, machine-readable instructions and a processor configured to execute the machine-readable instructions to:

create a thread pool for each work thread of a computer program, wherein each thread pool comprises a thread for each Instruction Set Architecture;

generate native code for at least one of the at least two ISAs for code segments of the computer program;

assign native code sequences to a corresponding thread in the thread pool for execution, with the native code sequences comprising the native code of the code segments; and

execute the native code sequences.

2 . The managing apparatus of claim 1 , wherein the machine-readable instructions comprise instructions to:

schedule a thread migration inside the thread pool, based on at least one of an instruction sequence, power characteristics and performance characteristics.

3 . The managing apparatus of claim 1 , wherein the machine-readable instructions comprise instructions to:

identify at least one safe-point in each work thread, wherein a safe-point is a point in a respective code sequence where an execution context can be safely synchronized.

4 . The managing apparatus of claim 3 , wherein

identifying at least one safe-point in each work thread is based on an analysis of an architecture independent virtual machine and the corresponding generated native code for the respective ISA.

5 . The managing apparatus of claim 3 , wherein the machine-readable instructions comprise instructions to:

assemble and/or manage the native code sequences between safe-points.

6 . The managing apparatus of claim 1 , wherein

the machine-readable instructions comprise code generation instructions for generating the native code.

7 . The managing apparatus of claim 1 , wherein

the native code sequences are targeted for a specific ISA.

8 . The managing apparatus of claim 1 , wherein

the native code sequences are targeted for a corresponding thread in the thread pool for execution by a thread scheduler of the managing apparatus.

9 . The managing apparatus of claim 1 , wherein

the machine-readable instructions comprise instructions to perform execution context management.

10 . The managing apparatus of claim 1 , wherein

the machine-readable instructions comprise instructions to manage execution contexts, the execution contexts each comprising an architecture-independent snapshot of an execution state of a respective work thread.

11 . A managing apparatus for a hybrid architecture containing cores with at least two different Instruction Set Architectures (ISAs), the managing apparatus comprising interface circuitry and processing circuitry configured to:

create a thread pool for each work thread of a computer program, wherein each thread pool comprises a thread for each Instruction Set Architecture;

generate native code for at least one of the at least two ISAs for code segments of the computer program;

assign native code sequences to a corresponding thread in the thread pool for execution, with the native code sequences comprising the native code of the code segments; and

execute the native code sequences.

12 . A managing device for a hybrid architecture containing cores with at least two different Instruction Set Architectures (ISAs), the managing device comprising means for communicating and means for processing for:

creating a thread pool for each work thread of a computer program, wherein each thread pool comprises a thread for each Instruction Set Architecture;

generating native code for at least one of the at least two ISAs for code segments of the computer program;

assigning native code sequences to a corresponding thread in the thread pool for execution; and

executing the code sequences.

13 . A managing method for managing a runtime system for a hybrid computing architecture containing cores with at least two different Instruction Set Architectures (ISAs), the method comprising:

creating a thread pool for each work thread of a computer program, wherein each thread pool comprises a thread for each Instruction Set Architecture;

generating native code for at least one of the at least two ISAs for code segments of the computer program;

assigning native code sequences to a corresponding thread in the thread pool for execution, with the native code sequences comprising the native code of the code segments; and

executing the code sequences.

14 . A non-transitory machine-readable storage medium including program code, when executed, to cause a machine to perform the method of claim 13 .