IP Library › Granted Patent US 12710944
Granted Patent B2
US 12710944 · App. 18/482,470 · Granted Aug 18, 2026

Target architecture determination

Inventor: John D. Leidel (McKinney, TX)
G06F8/447
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Quick Facts
Patent No.
US 12710944
App. No.
18/482,470
Granted
Aug 18, 2026
Kind
B2
Abstract

Examples of the present disclosure provide apparatuses and methods for target architecture determination. An example method comprises receiving an indication of a type of target architecture in a portion of source code and creating compiled code for the type of target architecture based on the indication.

Claims (26)

1 . An apparatus, comprising:

a processor;

a parser, wherein the processor is coupled to the parser and is configured to cause the parser to identify a first portion of source code suitable for a processor-in-memory (PIM) device coupled to the apparatus and identify a second portion of source code suitable for the processor based on a named address space defined in the source code; and

a code generator, wherein the processor is coupled to the code generator and is configured to cause the code generator to create a first portion of compiled code that includes first instructions for the PIM device based on the first portion of the source code and create a second portion of compiled code that includes second instructions for the processor based on the second portion of the source code.

2 . The apparatus of claim 1 , wherein the parser separates the source code into a number of portions based on a number of named address spaces including the named address space defined in the source code.

3 . The apparatus of claim 1 , wherein the first portion of complied code includes homogeneous instructions for the PIM device.

4 . The apparatus of claim 1 , wherein the PIM device is configured to execute only the first portion of compiled code.

5 . The apparatus of claim 1 , wherein the processor is configured to execute only the second portion of compiled code.

6 . A method, comprising:

creating, via a compiler, a first portion of compiled code that includes instructions for a processor-in-memory device (PIM) device based on a first portion of source code; and

creating, via the compiler, a second portion of compiled code that includes instructions for a base processor based on a second portion of the source code, wherein the second portion of compiled code includes a number of instructions for the base processor.

7 . The method of claim 6 , further including executing the first portion of compiled code by the PIM device.

8 . The method of claim 6 , further including executing the second portion of compiled code with the base processor.

9 . The method of claim 6 , wherein the first portion of compiled code includes a number of instructions for the PIM device.

10 . The method of claim 6 , wherein creating the first portion of compiled code includes determining that the first portion of source code is suitable for the PIM device based on a named address space defined in the first portion of the source code.

11 . The method of claim 10 , wherein the named address space includes an integer.

12 . The method of claim 6 , wherein the first portion of compiled code includes a number of homogeneous instructions.

13 . The method of claim 6 , further comprising creating a third portion of compiled code that includes instructions for a different target architecture.

14 . The method of claim 13 , wherein the third portion of compiled code is created in response to the source code having different named address spaces.

15 . An apparatus, comprising:

a processor; and

a code generator, wherein the processor is coupled to the code generator and is configured to cause the code generator to:

create first compiled code from a first portion of source code based on a named address space defined in the source code, the first compiled code comprising instructions for a processor-in-memory (PIM) device; and

create second compiled code from a second portion of the source code, the second compiled code comprising instructions for the processor.

16 . The apparatus of claim 15 , wherein the processor is coupled to a parser and the processor is configured to cause the parser to separate the first portion of source code from other portions of source code based on the named address space defined in the source code.

17 . The apparatus of claim 16 , wherein the processor is configured to cause the code generator to create the second compiled code from the second portion of the source code for the processor based on another named address space defined in the source code.