Chip set central processing unit cross reference code aligned basic input/output system for seamless boot
A firmware management operation. The firmware management operation includes identifying a processor environment installed on an information handling system from a plurality of processor environments, the processor environment comprising processor architecture, the processor architecture comprising a processor architecture version; providing the information handling system with a distributed BIOS, the distributed BIOS comprising a particular firmware configuration, the firmware particular configuration comprising a particular set of firmware components, the particular set of firmware components being based upon the processor architecture version; and, booting the information handling system using the particular firmware configuration based upon the processor architecture version.
1 . A computer-implementable method for performing a firmware management operation, comprising:
identifying a processor environment installed on an information handling system from a plurality of processor environments, the processor environment comprising a processor architecture, the processor architecture comprising at least one of a baseline processor architecture and a derived processor architecture;
performing a firmware compatibility management operation, the firmware compatibility management operation managing compatibility of a distributed BIOS to support a baseline processor architecture version of the distributed BIOS and a derived processor architecture version of the distributed BIOS, the baseline processor architecture version of the distributed BIOS including a baseline processor architecture firmware component, the derived processor architecture version including an associated best known configuration of a derived firmware component;
providing the information handling system with the distributed BIOS, the distributed BIOS comprising a particular firmware configuration, the particular firmware configuration comprising a particular set of firmware components, the particular set of firmware components being based upon at least one of the processor architecture version and the derived processor architecture version; and,
booting the information handling system using the particular firmware configuration based upon at least one of the baseline processor architecture and the derived processor architecture version.
2 . The method of claim 1 , wherein:
the baseline processor architecture version comprises comprising a referential starting point for creating a derivative thereof; and,
the information handling system comprises a baseline processor architecture processor chipset.
3 . The method of claim 2 , wherein:
the particular set of firmware components comprises a baseline configuration of chipset firmware components.
4 . The method of claim 3 , wherein:
the derived processor architecture is based upon the baseline processor architecture;
and,
the information handling system comprises a derived processor architecture processor chipset.
5 . The method of claim 4 , wherein:
the particular set of firmware components comprises a derived configuration of chipset firmware components.
6 . The method of claim 5 , wherein:
the derived configuration of chipset firmware components are generated via the firmware compatibility management operation.
7 . A system comprising:
a processor;
a data bus coupled to the processor; and
a non-transitory, computer-readable storage medium embodying computer program code, the non-transitory, computer-readable storage medium being coupled to the data bus, the computer program code interacting with a plurality of computer operations and comprising instructions executable by the processor and configured for:
identifying a processor environment installed on an information handling system from a plurality of processor environments, the processor environment comprising a processor architecture, the processor architecture comprising at least one of a baseline processor architecture and a derived processor architecture;
performing a firmware compatibility management operation, the firmware compatibility management operation managing compatibility of a distributed BIOS to support a baseline processor architecture version of the distributed BIOS and a derived processor architecture version of the distributed BIOS, the baseline processor architecture version of the distributed BIOS including a baseline processor architecture firmware component, the derived processor architecture version including an associated best known configuration of a derived firmware component;
providing the information handling system with the distributed BIOS, the distributed BIOS comprising a particular firmware configuration, the particular firmware configuration comprising a particular set of firmware components, the particular set of firmware components being based upon at least one of the processor architecture version and the derived processor architecture version; and,
booting the information handling system using the particular firmware configuration based upon at least one of the baseline processor architecture and the derived processor architecture version.
8 . The system of claim 7 , wherein:
the baseline processor architecture version comprises comprising a referential starting point for creating a derivative thereof; and,
the information handling system comprises a baseline processor architecture processor chipset.
9 . The system of claim 8 , wherein:
the particular set of firmware components comprises a baseline configuration of chipset firmware components.
10 . The system of claim 9 , wherein:
the derived processor architecture is based upon the baseline processor architecture; and,
the information handling system comprises a derived processor architecture processor chipset.
11 . The system of claim 10 , wherein:
the particular set of firmware components comprises a derived configuration of chipset firmware components.
12 . The system of claim 11 , wherein:
the derived configuration of chipset firmware components are generated via the firmware compatibility management operation.
13 . A non-transitory, computer-readable storage medium embodying computer program code, the computer program code comprising computer executable instructions configured for:
identifying a processor environment installed on an information handling system from a plurality of processor environments, the processor environment comprising a processor architecture, the processor architecture comprising at least one of a baseline processor architecture and a derived processor architecture;
performing a firmware compatibility management operation, the firmware compatibility management operation managing compatibility of a distributed BIOS to support a baseline processor architecture version of the distributed BIOS and a derived processor architecture version of the distributed BIOS, the baseline processor architecture version of the distributed BIOS including a baseline processor architecture firmware component, the derived processor architecture version including an associated best known configuration of a derived firmware component;
providing the information handling system with the distributed BIOS, the distributed BIOS comprising a particular firmware configuration, the particular firmware configuration comprising a particular set of firmware components, the particular set of firmware components being based upon at least one of the processor architecture version and the derived processor architecture version; and,
booting the information handling system using the particular firmware configuration based upon at least one of the baseline processor architecture and the derived processor architecture version.
14 . The non-transitory, computer-readable storage medium of claim 13 , wherein:
the baseline processor architecture version comprises comprising a referential starting point for creating a derivative thereof; and,
the information handling system comprises a baseline processor architecture processor chipset.
15 . The non-transitory, computer-readable storage medium of claim 14 , wherein:
the particular set of firmware components comprises a baseline configuration of chipset firmware components.
16 . The non-transitory, computer-readable storage medium of claim 15 , wherein:
the derived processor architecture is being based upon the baseline processor architecture; and,
the information handling system comprises a derived processor architecture processor chipset.
17 . The non-transitory, computer-readable storage medium of claim 16 , wherein:
the particular set of firmware components comprises a derived configuration of chipset firmware components.
18 . The non-transitory, computer-readable storage medium of claim 17 , wherein:
the derived configuration of chipset firmware components are generated via firmware compatibility management operation.
19 . The non-transitory, computer-readable storage medium of claim 13 , wherein:
the computer executable instructions are deployable to a client system from a server system at a remote location.
20 . The non-transitory, computer-readable storage medium of claim 13 , wherein:
the computer executable instructions are provided by a service provider to a user on an on-demand basis.