Processor power management using instruction throttling
An integrated circuit comprises a processor core including a processor pipeline configured to execute instructions; a register configured to store a power dial value that indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline; and an instruction throttling circuit configured to periodically stall removal of instructions from a queue in the processor pipeline for a number of clock cycles that is determined based on the power dial value.
1 . An integrated circuit for executing instructions comprising:
a processor core including a processor pipeline configured to execute instructions;
a register configured to store a power dial value that indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline;
a throttling control circuit configured to determine the power dial value based on a cache miss and a level of a cache in which the cache miss occurred, and store the power dial value in the register; and
an instruction throttling circuit configured to, responsive to an active cache miss, periodically stall removal of instructions from a queue in the processor pipeline for a number of clock cycles that is determined based on the power dial value.
2 . The integrated circuit of claim 1 , in which the register is part of a register file in the processor core.
3 . The integrated circuit of claim 1 , in which the queue is a fetch queue in a fetch stage of the processor pipeline.
4 . The integrated circuit of claim 1 , in which the queue is a decode queue in a decode stage of the processor pipeline.
5 . The integrated circuit of claim 1 , in which the queue is a dispatch queue in a dispatch stage of the processor pipeline.
6 . The integrated circuit of claim 1 , in which the queue is an issue queue in an issue stage of the processor pipeline.
7 . The integrated circuit of claim 1 , in which the queue is in a load-store unit of an execution stage of the processor pipeline.
8 . The integrated circuit of claim 1 , in which the queue is a retirement queue in a retire stage of the processor pipeline.
9 . The integrated circuit of claim 1 , in which the power dial value is determined to be proportional to the level of the cache in which the cache miss occurred.
10 . A method comprising:
determining, by a throttling control circuit, a power dial value based on a cache miss and a level of a cache in which the cache miss occurred;
writing, by the throttling control circuit, the power dial value to a register of a processor core including a processor pipeline configured to execute instructions, wherein the power dial value indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline; and
responsive to an active cache miss, stalling removal of instructions from a queue in the processor pipeline for a number of clock cycles that is determined based on the power dial value.
11 . The method of claim 10 , wherein determining the power dial value is further based on an estimate of current workload in the processor core.
12 . The method of claim 10 , in which stalling removal of instructions from the queue in the processor pipeline is responsive to an active translation lookaside buffer miss.
13 . The method of claim 10 , in which the queue is a decode queue in a decode stage of the processor pipeline.
14 . The method of claim 10 , in which the queue is a dispatch queue in a dispatch stage of the processor pipeline.
15 . An integrated circuit for executing instructions comprising:
a processor core including a processor pipeline configured to execute instructions;
a level-one cache configured to store data passing between the processor pipeline and an outer memory system;
a set of miss status holding registers that are each configured to store data describing a pending miss in the level-one cache;
a register configured to store a power dial value that indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline;
a throttling control circuit configured to determine the power dial value based on a cache miss and store the power dial value in the register; and
an instruction throttling circuit configured to periodically stall update of miss status holding registers in the set of miss status holding registers for a number of clock cycles that is determined based on the power dial value.
16 . The integrated circuit of claim 15 , in which the power dial value is determined to be proportional to a level of a cache in which the cache miss occurred.