Register configuration technique using metrics
Apparatuses, systems, and techniques to allocate and/or assign registers. In at least one embodiment, registers are allocated based, at least in part, on a set of estimated performance metrics associated with transformations generated prior to a register allocation phase of compilation.
1 . One or more processors, comprising:
circuitry to cause a first plurality of processor registers to be allocated to one or more software threads based, at least in part, on one or more computing performance metrics associated with a second plurality of registers allocated, wherein the computing performance metrics are to be measured before the first plurality of processor registers are allocated, and wherein:
the first and second pluralities of processor registers are configured as one or more processor register blocks;
each register block includes an equal number of registers; and
the first plurality of processor registers to be allocated is based, at least in part, on a number of the one or more software threads to be performed in parallel.
2 . The one or more processors of claim 1 ,
wherein the first plurality of processor registers to be allocated is based, at least in part, on one or more threshold values corresponding to the one or more computing performance metrics.
3 . The one or more processors of claim 1 ,
wherein the first plurality of processor registers to be allocated is based, at least in part, on one or more threshold numbers of processor register blocks.
4 . The one or more processors of claim 1 ,
wherein circuitry is to cause one or more instructions of an intermediate representation (IR) of a software program to be modified.
5 . The one or more processors of claim 1 ,
wherein the one or more computing performance metrics comprise values that indicate runtime of the one or more software threads.
6 . The one or more processors of claim 1 ,
wherein the first plurality of processor registers to be allocated is based, at least in part, on one or more other computing performance metrics associated with the first plurality of processor registers and are to be measured before the first plurality of processor registers are allocated.
7 . A system, comprising:
one or more circuits to cause a first plurality of processor registers to be allocated to one or more software threads based, at least in part, on one or more computing performance metrics associated with a second plurality of registers allocated, wherein the computing performance metrics are to be measured before the first plurality of processor registers are allocated, and wherein:
the first and second pluralities of processor registers are configured as one or more processor register blocks;
each register block includes an equal number of registers; and
the first plurality of processor registers to be allocated is based, at least in part, on a number of the one or more software threads to be performed in parallel.
8 . The system of claim 7 , wherein:
the first plurality of processor registers to be allocated is based, at least in part, on decreasing a number of register blocks to be used by the one or more software threads.
9 . The system of claim 8 , wherein the first plurality of processor registers to be allocated is based, at least in part, on one or more functions that estimate the one or more computing performance metrics.
10 . The system of claim 7 , wherein the first plurality of
processor registers to be allocated is based, at least in part, on a number of processor register blocks below one or more threshold numbers of processor register blocks.
11 . The system of claim 7 , wherein the first plurality of processor registers to be allocated is based, at least in part, on a data structure separate from an interference graph corresponding to an intermediate representation (IR) of a software program.
12 . The system of claim 7 , wherein the one or more computing performance metrics comprise values that indicate a number of spill instructions.
13 . The system of claim 7 , wherein the first plurality of
processor registers to be allocated is based, at least in part, on one or more modifications to one or more instructions of the one or more software threads.
14 . A method, comprising:
causing a first plurality of processor registers to be allocated to one or more software threads based, at least in part, on one or more computing performance metrics associated with a second plurality of registers allocated, wherein the computing performance metrics are to be measured before the first plurality of processor registers are allocated, and wherein:
the first and second pluralities of processor registers are configured as one or more processor register blocks;
each register block includes an equal number of registers; and
the first plurality of processor registers to be allocated is based, at least in part, on a number of the one or more software threads to be performed in parallel.
15 . The method of claim 14 , wherein:
the first plurality of processor registers to be allocated is based, at least in part, on decreasing a number of the register blocks to be used by the one or more software threads.
16 . The method of claim 14 , wherein the first plurality of processor registers to be allocated is based, at least in part, on one or more functions that estimate one or more computing performance metrics.
17 . The method of claim 14 , wherein the first plurality of
processor registers to be allocated is based, at least in part, on one or more numbers of processor register blocks required to perform the one or more software threads.
18 . The method of claim 14 , wherein the first plurality of processor registers to be allocated is based, at least in part, on reducing a number of processor registers required by the one or more software threads and exceeding one or more threshold performance values.
19 . The method of claim 14 , wherein the one or more computing performance metrics comprise one or more values that indicate a number of instructions to be inserted to perform the one or more software threads.