Error rates for memory with built in error correction and detection
The methods and systems improve uncorrectable error (UE) and silent data corruption (SDC) rates for memory chips and improve error correction of the memory chips. The systems include a memory bank with a plurality of memory chips in communication with a memory controller. The memory bank uses one additional memory chip that stores a bitwise parity of the data stored in the remaining memory chips of the memory bank. The parity bits are used to rebuild corrupted data when a UE occurs. The parity bits are also used to detect whether a SDC occurred in the data.
1 . A method, comprising:
receiving a read request for data, wherein a subset of a plurality of memory chips with built in error detection stores the data;
receiving in response to the read request, the data from the subset of the memory chips;
receiving parity bits, wherein one memory chip in the plurality of memory chips, different from the subset of the memory chips, stores the parity bits;
receiving an indication from any of the built in error detection of the plurality of memory chips that an uncorrectable error (UE) occurred in the data; and
rebuilding corrupted data by performing an exclusive OR operation using the parity bits by adding a one or a zero for a bit to result in an even parity where an even number of inputs are true in response to the exclusive OR operation.
2 . The method of claim 1 , further comprising:
identifying a memory chip that sent the indication that the UE occurred; and
generating recovered data for the memory chip by rebuilding the corrupted data for the memory chip using the parity bits.
3 . The method of claim 2 , wherein generating the recovered data further comprises:
performing the exclusive OR operation with the parity bits and the data from the plurality of memory chips that did not send the indication; and
adding, based on the exclusive OR operation, a one or a zero for a bit of the recovered data for the memory chip.
4 . The method of claim 2 , further comprising:
sending the recovered data.
5 . The method of claim 1 , further comprising:
outputting a result that the UE occurred indicating that the data is corrupted in response to determining that a plurality of memory chips sent indications that the UE occurred.
6 . The method of claim 1 , further comprising:
performing an exclusive OR operation of the data from the subset of the memory chips;
comparing an output of the exclusive OR operation with the parity bits;
identifying a silent data corruption occurred in the data in any of the plurality of memory chips based on a match not occurring between the output of the exclusive OR operation and the parity bits; and
outputting a result that the UE occurred indicating that the data is corrupted in response to identifying the silent data corruption occurred.
7 . The method of claim 1 , further comprising:
identifying a plurality of memory chips that sent the indication that the UE occurred;
identifying a silent data corruption occurred in the data in any of the plurality of memory chips; and
outputting a result that the UE occurred indicating that the data is corrupted.
8 . A system, comprising:
a plurality of memory chips with built in error detection, wherein a subset of the memory chips stores data and one memory chip different from the subset of the memory chips stores parity bits; and
a memory controller in communication with the plurality of memory chips, wherein the memory controller is operable to:
receive a read request for data;
receive in response to the read request, the data from the subset of the memory chips;
receive parity bits, wherein one memory chip in the plurality of memory chips, different from the subset of the memory chips, stores the parity bits;
receive an indication from any of the built in error detection of the plurality of memory chips that an uncorrectable error (UE) occurred in the data; and
rebuild corrupted data by performing an exclusive OR operation using the parity bits by adding a one or a zero for a bit to result in an even parity where an even number of inputs are true in response to the exclusive OR operation.
9 . The system of claim 8 , wherein the memory controller is further operable to:
identify a memory chip that sent the indication that the UE occurred; and
generate recovered data for the memory chip by rebuilding the corrupted data for the memory chip using the parity bits.
10 . The system of claim 9 , wherein the memory controller is further operable to generate the recovered data by:
performing the exclusive OR operation with the parity bits and the data from the plurality of memory chips that did not send the indication; and
adding, based on the exclusive OR operation, a one or a zero for a bit of the recovered data for the memory chip.
11 . The system of claim 9 , wherein the memory controller is further operable to:
send the recovered data.
12 . The system of claim 8 , wherein the memory controller is further operable to:
output a result that the UE occurred indicating that the data is corrupted in response to determining that a plurality of memory chips sent indications that the UE occurred.
13 . The system of claim 8 , wherein the memory controller is further operable to:
perform an exclusive OR operation of the data from the subset of the memory chips;
compare an output of the exclusive OR operation with the parity bits;
identify a silent data corruption occurred in the data in any of the plurality of memory chips based on a match not occurring between the output of the exclusive OR operation and the parity bits; and
output a result that the UE occurred indicating that the data is corrupted.
14 . The system of claim 8 , wherein the memory controller is further operable to:
identify a plurality of memory chips that sent the indication that the UE occurred;
identify a silent data corruption occurred in the data in any of the plurality of memory chips; and
output a result that the UE occurred indicating that the data is corrupted in response to identifying the silent data corruption occurred.
15 . A system, comprising:
a plurality of memory chips with built in error detection, wherein a subset of the memory chips stores data and one memory chip different from the subset of the memory chips stores parity bits; and
a memory controller in communication with the plurality of memory chips, wherein the memory controller is operable to:
receive a read request for data;
receive the data from the subset of the memory chips;
receive parity bits from the one memory chip different from the subset of the memory chips;
verify that an error notification was not received from the subset of the memory chips; and
verify whether a silent data corruption occurred in the data in any of the plurality of memory chips using the parity bits in a parity check.
16 . The system of claim 15 , wherein the memory controller is further operable to verify whether the silent data corruption occurred by:
performing an exclusive OR operation of the data from the subset of the memory chips; and
comparing an output of the exclusive OR operation with the parity bits.
17 . The system of claim 16 , wherein the memory controller is further operable to:
send a result that an uncorrectable error (UE) occurred indicating that the data is corrupted based on a match not occurring between the output of the exclusive OR operation and the parity bits.
18 . The system of claim 16 , wherein the memory controller is further operable to:
send a result indicating that a match occurred between the output of the exclusive OR operation and the parity bits.
19 . The system of claim 18 , wherein the memory controller is further operable to complete the read request in response to the result.
20 . The system of claim 16 , wherein the memory controller is further operable to:
identify multiple silent data corruptions occurred in a plurality of chip in response to performing the exclusive OR operation; and
send a result that an uncorrectable error (UE) occurred indicating that the data is corrupted based on identifying multiple silent data corruptions occurred.