System-on-chip for synchronizing data between processors and memory sharing method thereof

1 . A system-on-chip (SoC) comprising:

a host comprising at least one processing unit configured to generate a job launching;

a buffer memory;

a producer configured to generate data in response to the job launching and store the generated data in the buffer memory;

a consumer configured to read and process the data from the buffer memory in response to the job launching; and

a HiveSync monitor configured to (i) subdivide memory areas of the buffer memory into a plurality of fine units, and (ii) exchange with the producer and the consumer, at least one ready bit indicating a readiness state of data stored in at least one fine unit of the plurality of fine units of the buffer memory,

wherein the HiveSync monitor device comprises:

a static random access memory (SRAM) configured to store and update a readiness table that includes the at least one ready bit for a physical address of the at least one fine unit; and

circuitry configured to manage the readiness table according to an access request from the producer or the consumer, wherein the readiness table arranges the at least one ready bit in a cache-line format.

2 . The SoC of claim 1 , wherein the at least one ready bit is provided as 1-bit per 64-bytes of the data.

3 . The SoC of claim 1 , wherein the circuitry is further

configured to:

determine a validity of the physical address using tag of the physical address;

output or wait for the at least one ready bit according to a value of the at least one ready bit when receiving a read request from the consumer;

write the value of the at least one ready bit according to a request from the producer or the consumer; and

back up or write back the readiness table to the buffer memory.

4 . The SoC of claim 1 , wherein the physical address includes a HiveSync attribute bit indicating whether the HiveSync monitor is subject to ready bit management.

5 . The SoC of claim 4 , wherein, when the HiveSync attribute bit is logic ‘1’, the physical address is managed as the readiness table in the HiveSync monitor.

6 . The SoC of claim 1 , wherein the consumer includes at least two processors that read the data from the buffer memory and process the read data.

7 . The SoC of claim 5 , wherein the at least two processors read the data from the buffer memory using the HiveSync monitor without intervention of the host after the job launching.

8 . A method of synchronizing a buffer memory of system-on-chip (SoC), comprising:

writing, by a producer, data into a buffer memory;

issuing, by the producer, a request to write a ready bit for the data to a HiveSync monitor; and

issuing, by a consumer, a read request for the ready bit to the HiveSync monitor,

wherein, when the ready bit indicates a ready state, the consumer issues a read request for the data to the buffer memory,

wherein, when the ready bit indicates an unready state, the consumer issues an interrupt request to the HiveSync monitor, and the HiveSync monitor transmits an interrupt to the consumer in response to the interrupt request.

9 . The method of claim 8 , wherein the ready bit is allocated as 1 bit per 64-byte of the data stored in the buffer memory.

10 . The method of claim 8 , further comprising issuing, by the consumer, a read request for the ready bit to the HiveSync monitor in response to the interrupt.

11 . The method of claim 8 , wherein the ready bit consists of multi-bits indicating three or more readiness states.

12 . The method of claim 11 , wherein the readiness states include a start state, number of consumers for the data, a discard state, and an end state.

13 . A system-on-a-chip (SoC) comprising:

a host comprising at least one processing unit configured to generate a job launching;

a buffer memory;

a first processor configured to generate data in response to the job launching and store the generated data in the buffer memory;

a second processor configured to read and process the data from the buffer memory in response to the job launching;

a third processor configured to read and process the data from the buffer memory in response to the job launching;

a HiveSync monitor configured to exchange ready bit indicating a readiness state of the data in the buffer memory, the first processor, the second processor, and the third processor; and

a system interconnector configured to provide a communication channel for each of the host, the buffer memory, the first processor, the second processor, the third processor, and the HiveSync monitor,

wherein the ready bit is allocated as 1 bit per specific size unit of the data stored in the buffer memory,

the HiveSync monitor is configured to establish a readiness table that manages the ready bit according to requests from the first processor, the second processor, and the third processor, and

based on the ready bit of the data requested by the second processor or the third processor transitioning from logic ‘0’ to logic ‘1’, the HiveSync monitor is configured to generate and send an interrupt to the second processor or the third processor.

14 . The SoC of claim 13 , wherein the specific size corresponds to 32-bytes or 64-bytes.