IP Library › Granted Patent US 12711058

Granted Patent B2

US 12711058 · App. 18/597,067 · Granted Aug 18, 2026

Memory system, operation method thereof, electronic apparatus, and computer readable storage medium

Inventors: Hai Fu (Wuhan, CN); Hongbo Wang (Wuhan, CN)

Assignee: Yangtze Memory Technologies Co., Ltd.

G06F12/0246 G06F2212/7201

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Quick Facts

Patent No.: US 12711058
App. No.: 18/597,067
Granted: Aug 18, 2026
Kind: B2

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Abstract

A memory system includes: a memory device and a memory controller coupled with the memory device, wherein the memory device includes a plurality of first subregions storing mapping data; the memory controller is coupled with a host; the host includes a plurality of second subregions corresponding to the plurality of first subregions; the mapping data includes a logical address to physical address mapping relationship; logical address ranges of mapping data stored in a first subregion and a second subregion corresponding to each other are the same; the memory controller is configured to: divide the first subregion into a plurality of data units; when mapping data in a data unit is changed, label the data unit; and based on the number of the labeled data units in the first subregion, determine whether to trigger an update of mapping data in the second subregion corresponding to the first subregion.

Claims (78)

1 . A memory system, comprising:

a memory device comprising a plurality of first subregions storing mapping data; and

a memory controller coupled with the memory device and coupled with a host,

wherein:

the host comprises a plurality of second subregions corresponding to the plurality of first subregions;

the mapping data comprises a logical address to physical address mapping relationship; and

logical address ranges of mapping data stored in a first subregion and a second subregion corresponding to each other are the same; and

wherein the memory controller is configured to:

establish a bit map for the first subregion with one bit in the bit map corresponding to one of a plurality of data units in the first subregion to divide the first subregion into the plurality of data units;

when a physical address corresponding to at least one logical address in a data unit is changed, label a bit corresponding to the data unit in the bit map as a dirty unit; and

based on a number of the labeled data units in the first subregion according to corresponding bits of the bit map, compare the number of the labeled data units with an update threshold and determine whether to trigger an update of mapping data in the second subregion corresponding to the first subregion based on the comparison.

2 . The memory system of claim 1 , wherein the memory controller is configured to:

establish a bit map for the first subregion, with one bit in the bit map corresponding to one of the data units in the first subregion, so as to divide the first subregion into the plurality of data units; and

when a physical address corresponding to at least one logical address in the data unit is changed, label a bit corresponding to the data unit in the bit map, so as to label the data unit.

3 . The memory system of claim 1 , wherein the memory controller is configured to:

when the number of the labeled data units in the first subregion is greater than or equal to an update threshold, determine to trigger the update of the mapping data in the second subregion corresponding to the first subregion; and

when the number of the labeled data units in the first subregion is less than the update threshold, determine not to trigger the update of the mapping data in the second subregion corresponding to the first subregion.

4 . The memory system of claim 1 , wherein the memory controller is further configured to:

receive a read command packet;

when the read command packet comprises the mapping data in the second subregion, acquire the number of the labeled data units in the first subregion corresponding to the second subregion; and

in response to determination of triggering the update of the mapping data in the second subregion corresponding to the first subregion, send a message of recommending an update of the second subregion.

5 . The memory system of claim 4 , wherein the memory controller is further configured to:

when a logical address of the mapping data in the read command packet falls within a logical address range of the mapping data stored in the labeled data units, acquire a physical address corresponding to the logical address from the first subregion and perform a read operation; and

when the logical address of the mapping data in the read command packet falls outside the logical address range of the mapping data stored in the labeled data units, perform a read operation based on a physical address in the read command packet.

6 . The memory system of claim 4 , wherein the memory controller is further configured to:

in response to determination of updating the mapping data in the second subregion, send the mapping data stored in the first subregion corresponding to the second subregion.

7 . The memory system of claim 3 , wherein the number of the data units in the first subregion ranges from 8 to 1024, and a ratio of the update threshold to the number of the data units in the first subregion ranges from 25% to 75%.

8 . An operation method of a memory system, comprising:

establish a bit map for a first subregion storing mapping data in a memory device of the memory system with one bit in the bit map corresponding to one of a plurality of data units in the first subregion to divide the first subregion into the plurality of data units;

when a physical address corresponding to at least one logical address in a data unit is changed, label a bit corresponding to the data unit in the bit map as a dirty unit, wherein the mapping data comprises a logical address to physical address mapping relationship; and

based on the number of the labeled data units in the first subregion according to corresponding bits of the bit map, comparing the number of the labeled data units with an update threshold and determining whether to trigger an update of mapping data in a second subregion corresponding to the first subregion in a host based on the comparison, wherein logical address ranges of mapping data stored in the first subregion and the second subregion corresponding to each other are the same.

9 . The operation method of the memory system of claim 8 , wherein the dividing the first subregion storing the mapping data in the memory device into the plurality of data units and labeling the data unit comprises:

establishing a bit map for the first subregion, with one bit in the bit map corresponding to one of the data units in the first subregion, so as to divide the first subregion into the plurality of data units; and

when a physical address corresponding to at least one logical address in the data unit is changed, labeling a bit corresponding to the data unit in the bit map, so as to label the data unit.

10 . The operation method of the memory system of claim 8 , wherein the determining whether to trigger the update of the mapping data in the second subregion corresponding to the first subregion in the host comprises:

when the number of the labeled data units in the first subregion is greater than or equal to an update threshold, determining to trigger the update of the mapping data in the second subregion corresponding to the first subregion; and

when the number of the labeled data units in the first subregion is less than the update threshold, determining not to trigger the update of the mapping data in the second subregion corresponding to the first subregion.

11 . The operation method of the memory system of claim 8 , further comprising:

receiving a read command packet;

when the read command packet comprises the mapping data in the second subregion, acquiring the number of the labeled data units in the first subregion corresponding to the second subregion; and

in response to determination of triggering the update of the mapping data in the second subregion corresponding to the first subregion, sending a message of recommending an update of the second subregion.

12 . The operation method of the memory system of claim 11 , further comprising:

when a logical address of the mapping data in the read command packet falls within a logical address range of the mapping data stored in the labeled data units, acquiring a physical address corresponding to the logical address from the first subregion and performing a read operation; and

when the logical address of the mapping data in the read command packet falls outside the logical address range of the mapping data stored in the labeled data units, performing a read operation based on a physical address in the read command packet.

13 . The operation method of the memory system of claim 11 , further comprising:

in response to determination of updating the mapping data in the second subregion, sending the mapping data stored in the first subregion corresponding to the second subregion.

14 . An electronic apparatus, comprising:

a memory system comprising a memory device and a memory controller coupled to the memory device; and

a host coupled to the memory system,

wherein:

the memory device comprises a plurality of first subregions storing mapping data;

the host comprises a host controller and a plurality of second subregions corresponding to the plurality of first subregions;

the mapping data comprises a logical address to physical address mapping relationship; and

logical address ranges of mapping data stored in a first subregion and a second subregion corresponding to each other are the same; and

wherein the memory controller is configured to:

when a physical address corresponding to at least one logical address in a data unit is changed, label a bit corresponding to the data unit in the bit map as a dirty unit;

wherein the host controller is configured to:

receive the message of recommending the update of the second subregion; and

determine whether to update the mapping data in the second subregion.

15 . The electronic apparatus of claim 14 , wherein the memory controller is configured to:

when a physical address corresponding to at least one logical address in the data unit is changed, label a bit corresponding to the data unit in the bit map, so as to label the data unit.

16 . The electronic apparatus of claim 14 , wherein the memory controller is configured to:

17 . The electronic apparatus of claim 14 , wherein the host controller is further configured to:

send a read command packet to the memory controller; and

the memory controller is further configured to:

receive the read command packet, and

when the read command packet comprises the mapping data in the second subregion, acquire the number of the labeled data units in the first subregion corresponding to the second subregion.

18 . The electronic apparatus of claim 14 , wherein the memory controller is further configured to:

in response to determination of updating the mapping data in the second subregion by the host controller, send the mapping data stored in the first subregion corresponding to the second subregion;

the host controller is further configured to:

receive the mapping data stored in the first subregion, and

update the mapping data in the second subregion corresponding to the first subregion.