Memory devices, operating methods and memory systems for managing bad memory blocks

1 . A memory device, comprising:

a memory cell array including: a first memory block; and

a peripheral circuit coupled with the first memory block and configured to:

receive a first block address information of the first memory block;

determine whether the first memory block is a bad block according to the first block address information;

generate a first indication signal in response to the first memory block being determined as the bad block; and

stop an activation of the first memory block pointed to by the first block address information in response to the first indication signal.

2 . The memory device of claim 1 , wherein the memory cell array further includes: at least one redundant memory block for replacing a bad block; and

the peripheral circuit is further configured to: determine a block address information pointing to a certain redundant memory block in response to the first memory block being determined as the bad block; and activate the certain redundant memory block to replace the first memory block.

3 . The memory device of claim 1 , wherein the peripheral circuit is further configured to:

compare each of stored at least one piece of reference address information with the first block address information, wherein one piece of the reference address information is configured to point to one bad block in the memory device;

generate a first marking signal in response to the first block address information being identical to a first reference address information, wherein the first marking signal is configured to indicate the first memory block as the bad block; and

generate the first indication signal in response to the first marking signal.

4 . The memory device of claim 3 , wherein the peripheral circuit is further configured to:

compare each reference bit in each of the at least one piece of reference address information with a corresponding bit in the first block address information; and

generate the first marking signal in response to each reference bit in the first reference address information being identical to each corresponding bit in the first block address information.

5 . The memory device of claim 3 , wherein the memory cell array includes: a second memory block, wherein the second memory block is one of at least one redundant memory block for replacing a bad block retained in the memory device; and the peripheral circuit is further configured to: generate a first control code in response to the first marking signal; and parse the first control code to obtain a second block address information pointing to the second memory block.

6 . The memory device of claim 3 , wherein the memory cell array further includes: a third memory block; and the peripheral circuit is further configured to:

receive a third block address information of the third memory block;

determine whether the third memory block is a bad block according to the third block address information;

generate a second indication signal in response to the third memory block being determined as the bad block; and

stop activation of the third memory block pointed to by the third block address information in response to the second indication signal.

7 . The memory device of claim 6 , wherein the peripheral circuit is further configured to:

compare each of the at least one piece of reference address information with the third block address information, and generate a second marking signal in response to the third block address information being identical to a second reference address information, wherein the second marking signal is configured to indicate the third memory block as a bad block; and

generate the second indication signal in response to the second marking signal.

8 . The memory device of claim 7 , wherein the memory cell array includes: a fourth memory block, wherein the fourth memory block is one of at least one redundant memory block for replacing a bad block retained in the memory device; and the peripheral circuit is further configured to:

generate a second control code in response to the second marking signal; and

parse the second control code to obtain a fourth block address information pointing to the fourth memory block.

9 . An operating method of a memory device, the operating method comprising:

receiving a first block address information, and determining whether a first memory block pointed to by the first block address information is a bad block according to the first block address information;

generating a first indication signal in response to the first memory block being determined as the bad block; and

stopping an activation of the first memory block pointed to by the first block address information in response to the first indication signal.

10 . The method of claim 9 , further including:

determining a second block address information in response to the first memory block being determined as the bad block; and

activating a second memory block pointed to by the second block address information to replace the first memory block,

wherein the second memory block is one of at least one redundant memory block for replacing a bad block retained in the memory device.

11 . The method of claim 9 , wherein the determining whether the first memory block pointed to by the first block address information is the bad block according to the first block address information includes:

comparing each of stored at least one piece of reference address information with the first block address information, wherein one piece of the reference address information is configured to point to one bad block in the memory device; and

generating a first marking signal in response to the first block address information being identical to a first reference address information, wherein the first marking signal is configured to indicate the first memory block as the bad block.

12 . The method of claim 11 , wherein the comparing each of the stored at least one piece of reference address information with the first block address information includes:

comparing each reference bit in each of the at least one piece of reference address information with a corresponding bit in the first block address information; and

the generating the first marking signal in response to the first block address information being identical to first reference address information includes:

generating the first marking signal in response to each reference bit in the first reference address information being identical to each corresponding bit in the first block address information.

13 . The method of claim 10 , wherein the determining the second block address information includes:

generating a first control code in response to the first memory block being determined as the bad block; and

parsing the first control code to obtain the second block address information pointing to the second memory block.

14 . The method of claim 9 , wherein the first memory block is stored in a memory cell array and the memory cell array includes:

at least one redundant memory block for replacing thee bad block; and

the method includes:

determining a block address information pointing to a certain redundant memory block in response to the first memory block being determined as the bad block; and

activating the certain redundant memory block to replace the first memory block.

15 . A non-transitory computer readable medium comprising instructions to cause programmable circuitry to:

determine whether a first memory block pointed to by a first block address information is a bad block according to the first block address information;

generate a first indication signal in response to the first memory block being determined as the bad block; and

stop an activation of the first memory block pointed to by the first block address information in response to the first indication signal.

16 . The non-transitory computer readable medium of claim 15 , wherein the instructions cause the programmable circuitry to:

determine a second block address information in response to the first memory block being determined as the bad block; and

activate a second memory block pointed to by the second block address information to replace the first memory block,

wherein the second memory block is one of at least one redundant memory block for replacing a bad block.

17 . The non-transitory computer readable medium of claim 16 , wherein the instructions cause the programmable circuitry to determine the second block address information by:

generating a first control code in response to the first memory block being determined as the bad block; and

parsing the first control code to obtain the second block address information pointing to the second memory block.

18 . The non-transitory computer readable medium of claim 15 , wherein the instructions cause the programmable circuitry to determine whether the first memory block pointed to by the first block address information is the bad block according to the first block address information by:

comparing each of stored at least one piece of reference address information with the first block address information, wherein one piece of the reference address information is configured to point to one bad block; and

generating a first marking signal in response to the first block address information being identical to a first reference address information, wherein the first marking signal is configured to indicate the first memory block as the bad block.

19 . The non-transitory computer readable medium of claim 18 , wherein the instructions cause the programmable circuitry to compare each of the stored at least one piece of reference address information with the first block address information by:

comparing each reference bit in each of the at least one piece of reference address information with a corresponding bit in the first block address information; and

the generating the first marking signal in response to the first block address information being identical to first reference address information includes:

generating the first marking signal in response to each reference bit in the first reference address information being identical to each corresponding bit in the first block address information.

20 . The non-transitory computer readable medium device of claim 15 , wherein the first memory block is stored in a memory cell array and the memory cell array includes:

at least one redundant memory block for replacing thee bad block; and

wherein the instructions cause the programmable circuitry to:

determine a block address information pointing to a certain redundant memory block in response to the first memory block being determined as the bad block; and

activate the certain redundant memory block to replace the first memory block.