Memory management among multiple erase blocks coupled to a same string
An apparatus can comprise a memory array comprising a plurality of physical blocks of strings of memory cells, wherein each physical block of the plurality of physical blocks comprises multiple erase blocks that are independently erasable, and wherein the multiple erase blocks within a particular physical block comprise memory cells coupled to a same string corresponding to the particular physical block. A controller can be coupled to the memory array and configured to: perform a memory management operation at an erase block level; and switch to perform the memory management operation at a physical block level.
1 . An apparatus, comprising:
a memory array comprising a plurality of physical blocks of strings of memory cells, wherein each physical block of the plurality of physical blocks comprises multiple erase blocks that are independently erasable, and wherein the multiple erase blocks within a particular physical block comprise memory cells coupled to a same string corresponding to the particular physical block; and
a controller coupled to the memory array and configured to:
perform a memory management operation at an erase block level;
switch between performing the memory management operation at the erase block level and at a physical block level in accordance with a memory management policy that includes a particular frequency at which the memory management operation is performed at the physical block level;
wherein the particular frequency is a variable frequency, and wherein the variable frequency is a function of an erase block program/erase (P/E) cycling offset value associated with the memory array and of an amount of valid data per physical block.
2 . The apparatus of claim 1 , wherein the memory management operation is a garbage collection operation.
3 . The apparatus of claim 1 , wherein each physical block of the memory array comprises at least three erase blocks that are independently erasable.
4 . The apparatus of claim 1 , wherein the memory array comprises a three-dimensional replacement gate NAND array.
5 . An apparatus, comprising:
a memory array comprising a plurality of physical blocks of strings of memory cells, wherein each physical block of the plurality of physical blocks comprises multiple erase blocks that are independently erasable, and wherein the multiple erase blocks within a particular physical block comprise memory cells coupled to a same string corresponding to the particular physical block; and
a controller coupled to the memory array and configured to:
track a program/erase (P/E) cycling offset for the multiple erase blocks;
perform garbage collection on a per erase block basis;
determine an amount of valid data on a per physical block basis; and
periodically switch to perform garbage collection on a per physical block basis instead of on a per erase block basis;
wherein a frequency at which the controller periodically switches to perform garbage collection on the per physical block basis is variable; and
wherein the frequency is a function of the P/E cycling offset and of the determined amount of valid data on the per physical block basis.
6 . The apparatus of claim 5 , wherein at least one of the physical blocks includes a number of dummy word lines separating at least two multiple erase blocks within the at least one physical block.
7 . A method, comprising:
tracking a program/erase (P/E) cycling offset for multiple erase blocks of a memory array comprising a plurality of physical blocks of strings of memory cells, wherein each physical block of the plurality of physical blocks comprises multiple erase blocks that are independently erasable, and wherein the multiple erase blocks within a particular physical block comprise memory cells coupled to a same string corresponding to the particular physical block;
performing garbage collection on a per erase block basis; and
periodically switching to performing the garbage collection on the per physical block basis instead of on the per erase block basis,
wherein a frequency at which the periodically switching occurs is a function of a P/E cycling offset of the multiple erase blocks and of a determined amount of valid data on a per physical block basis.
8 . The method of claim 7 , further comprising, after switching to performing garbage collection on the per physical block basis instead of on the per erase block basis, switching back to performing garbage collection on the per erase block basis.