Configurable in memory computing engine, platform, bit cells and layouts therefore
Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.
1 . A device, comprising:
a compute-in-memory (CIM) array of bit-cells configured to receive parallel bitwise input signals via a first CIM array dimension and to receive one or more accumulation signals via a second CIM array dimension, wherein each of a plurality of bitcells associated with a common analog accumulation signal forms a respective CIM channel configured to provide analog representation of a respective portion of a multi-bit computation output signal, the CIM array configured to perform a multi-bit computing operation on the input and accumulation signals using single-bit internal circuits and signals,
wherein the multi-bit computing operation of the CIM array comprises bit-parallel/bit-serial (BPBS) computing, and
wherein the bit-parallel computing comprises:
loading different matrix-element bits into respective in-memory computing channels;
using respective barrel shifters, barrel shifting digitized outputs from the in-memory computing channels to implement corresponding bit weightings; and
using respective accumulators, performing digital accumulation over all of the computing channels to yield a multi-bit matrix-element compute result.
2 . The device of claim 1 , wherein the bit-serial computing comprises:
individually applying each bit of a vector element to the loaded matrix element bits and storing each resulting digitized output; and
using respective barrel shifters, barrel shifting the stored digitized outputs associated with each vector element bit prior to a digital accumulation with stored digitized outputs corresponding to subsequent input vector bits.
3 . The device of claim 1 , further comprising a reshaping buffer, configured to reshape a sequence of received data words to form the parallel bitwise input signals.
4 . The device of claim 1 , further comprising:
analog-to-digital converter (ADC) circuitry configured to process the plurality of CIM channel output signals to provide thereby a sequence of multi-bit output words.
5 . The device of claim 1 , further comprising a sparsity controller configured to mask zero-valued elements of the parallel bit-wise input signals, and to avoid, by the multi-bit computing operation, processing zero-valued elements of the parallel bit-wise input signals.
6 . A device, comprising:
a compute-in-memory (CIM) array of bit-cells configured to receive parallel bitwise input signals via a first CIM array dimension and to receive one or more accumulation signals via a second CIM array dimension, wherein each of a plurality of bitcells associated with a common analog accumulation signal forms a respective CIM channel configured to provide analog representation of a respective portion of a multi-bit computation output signal, the CIM array configured to perform a multi-bit computing operation on the input and accumulation signals using single-bit internal circuits and signals,
wherein the multi-bit computing operation of the CIM array comprises bit-parallel/bit-serial (BPBS) computing, and
wherein the bit-serial computing comprises:
individually applying each bit of a vector element to the loaded matrix element bits and storing each resulting digitized output; and
using respective barrel shifters, barrel shifting the stored digitized outputs associated with each vector element bit prior to a digital accumulation with stored digitized outputs corresponding to subsequent input vector bits.
7 . The device of claim 6 , further comprising a reshaping buffer, configured to reshape a sequence of received data words to form the parallel bitwise input signals.
8 . The device of claim 7 , wherein the reshaping buffer is configured to enable reuse and shifting of input data in accordance with convolutional neural-network operations.
9 . The device of claim 6 , further comprising:
analog-to-digital converter (ADC) circuitry configured to process the plurality of CIM channel output signals to provide thereby a sequence of multi-bit output words.
10 . The device of claim 6 , further comprising a sparsity controller configured to mask zero-valued elements of the parallel bit-wise input signals, and to avoid, by the multi-bit computing operation, processing zero-valued elements of the parallel bit-wise input signals.
11 . A method, comprising:
performing a multi-bit computing operation by a compute-in-memory (CIM) array, the CIM array including bit-cells configured to receive parallel bitwise input signals via a first CIM array dimension and to receive one or more accumulation signals via a second CIM array dimension, wherein each of a plurality of bitcells associated with a common analog accumulation signal forms a respective CIM channel configured to provide analog representation of a respective portion of a multi-bit computation output signal,
wherein the multi-bit computing operation includes at least one of bit-parallel computing or bit-serial computing,
wherein the bit-parallel computing comprises:
loading different matrix-element bits into respective in-memory computing channels;
using respective barrel shifters, barrel shifting digitized outputs from the in-memory computing channels to implement thereby corresponding bit weightings; and
using respective accumulators, performing digital accumulation over all of the computing channels to yield a multi-bit matrix-element compute result, and
wherein the bit-serial computing comprises:
individually applying each bit of a vector element to the loaded matrix element bits and storing each resulting digitized output; and
using respective barrel shifters, barrel shifting the stored digitized outputs associated with each vector element bit prior to a digital accumulation with stored digitized outputs corresponding to subsequent input vector bits.
12 . The method of claim 11 , further comprising:
reshaping, by a reshaping buffer, a sequence of received data words to form the parallel bitwise input signals.
13 . The method of claim 11 , further comprising:
providing a sequence of multi-bit output words by processing the plurality of CIM channel output signals by analog-to-digital converter (ADC) circuitry.
14 . The method of claim 13 , further comprising:
providing, by a near-memory computing path, the sequence of multi-bit output words as a computing result.
15 . The method of claim 13 , wherein the processing the plurality of CIM channel output signals by the ADC circuitry comprises, for each CIM channel:
digitizing the CIM channel output signal, and
imparting a respective binary weighting to the digitized CIM channel output signal, thereby forming a respective portion of a multi-bit output word.
16 . The method of claim 13 , wherein the processing the plurality of CIM channel output signals by the ADC circuitry comprises, for each of a plurality of subsets of the CIM channels:
digitizing a weighted analog summation of the CIM channel output signals of the respective subset of CIM channels to form thereby a respective portion of a multi-bit output word.
17 . The method of claim 11 , further comprising:
masking, by a sparsity controller, zero-valued elements of the parallel bit-wise input signals.
18 . The method of claim 11 , further comprising:
controlling, by a configurable finite-state machine (FSM), the multi-bit computing operation.
19 . The method of claim 18 , wherein the controlling the multi-bit computing operation includes at least one of:
controlling, by the FSM, parallel computing hardware utilized by at least one of the CIM channels, or
controlling, by the FSM, computations based on instructions loaded in a local memory.
20 . The method of claim 19 , wherein the multi-bit computing operation includes the bit-parallel computing and the bit-serial computing.