Power loss protection in memory sub-systems
Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.
1 . A system comprising:
a plurality of memory components comprising non-volatile memory components and a volatile cache; and
a processing device, operatively coupled with the plurality of memory components, configured to perform operations comprising:
detecting data written to the volatile cache;
identifying, from among multiple portions of the non-volatile memory components, a portion having a lower program latency relative to other portions of the non-volatile memory components based on a ranking of program latency of the multiple portions;
accessing the data written to the volatile cache; and
moving the data to the portion of the non-volatile memory components.
2 . The system of claim 1 , wherein the identifying the portion of the non-volatile memory components based on the ranking includes:
performing a performance test upon the non-volatile memory components, the performance test including a latency test; and
determining the program latency of each of the multiple portions based on the latency test.
3 . The system of claim 2 , wherein the latency test comprises determining a program time (tPROG) for each of the multiple portions.
4 . The system of claim 1 , wherein the identified portion comprises a single-level cell NAND flash memory.
5 . The system of claim 1 , wherein the portion of the non-volatile memory components is a first portion of the multiple portions, and the operations further comprise:
performing a latency test on the first portion;
determining that a program latency of the first portion exceeds a threshold;
identifying a second portion of the multiple portions having a lower program latency than the first portion;
moving the data to the second portion.
6 . The system of claim 1 , wherein the accessing the data written to the volatile cache includes:
detecting a trigger event; and
accessing the data responsive to the trigger event.
7 . The system of claim 6 , wherein the trigger event includes an asynchronous power loss.
8 . A method comprising:
a plurality of memory components comprising non-volatile memory components and a volatile cache; and
a processing device, operatively coupled with the plurality of memory components, configured to perform operations comprising:
detecting data written to the volatile cache;
identifying, from among multiple portions of the non-volatile memory components, a portion having a lower program latency relative to other portions of the non-volatile memory components based on a ranking of program latency of the multiple portions;
accessing the data written to the volatile cache; and
moving the data to the portion of the non-volatile memory components.
9 . The method of claim 8 , wherein the ranking the program latency comprises:
performing a performance test upon the non-volatile memory components, the performance test including a latency test; and
determining a program latency for each of the multiple portions based on the latency test.
10 . The method of claim 9 , wherein the performing the latency-test includes determining a program time (tPROG) for each of the multiple portions.
11 . The method of claim 8 , wherein the identified portion comprises a single-level cell (SLC) region of the non-volatile memory components.
12 . The method of claim 8 , wherein the portion of the non-volatile memory components is a first portion, and the operations further comprise:
performing a latency test on the first portion;
determining that a program latency of the first portion exceeds a threshold;
identifying a second portion of the multiple portions having a lower program latency than the first portion; and
moving the data to the second portion.
13 . The method of claim 8 , wherein the accessing the data written to the volatile cache includes:
detecting a trigger event; and
accessing the data written responsive to the trigger event.
14 . The method of claim 13 , wherein the trigger event includes an asynchronous power loss.
15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
a plurality of memory components comprising non-volatile memory components and a volatile cache; and
a processing device, operatively coupled with the plurality of memory components, configured to perform operations comprising:
detecting data written to the volatile cache;
identifying, from among multiple portions of the non-volatile memory components, a portion having a lower program latency relative to other portions of the non-volatile memory components based on a ranking of program latency of the multiple portions;
accessing the data written to the volatile cache; and
moving the data to the portion of the non-volatile memory components.
16 . The non-transitory computer-readable storage medium of claim 15 , wherein the identifying the portion of the non-volatile memory components based on the ranking includes:
performing a performance test upon the non-volatile memory components, the performance test including a latency test; and
determining the program latency of each of the multiple portions based on the latency test.
17 . The non-transitory computer-readable storage medium of claim 16 , wherein the latency test comprises determining a program time (tPROG) for each of the multiple portions.
18 . The non-transitory computer-readable storage medium of claim 15 , wherein the identified portion comprises a single-level cell.
19 . The non-transitory computer-readable storage medium of claim 15 , wherein the portion of the non-volatile memory components is a first portion of the multiple portions, and the operations further comprise:
performing a latency test on the first portion;
determining that a program latency of the first portion exceeds a threshold;
identifying a second portion of the multiple portions having a lower program latency than the first portion; and
moving the data to the second portion.
20 . The non-transitory computer-readable storage medium of claim 15 , wherein the accessing the data written to the volatile cache includes:
detecting a trigger event; and
accessing the data responsive to the trigger event.