Hardware pipeline for cache coherent interconnect including snoop filters
A hardware-implemented pipeline for a set-associative snoop filter includes a syndrome generator circuit configured to receive a way entry including raw data and raw check bits, and generate a syndrome from the raw data and the raw check bits. The pipeline further includes a buffer configured to store the raw data, the raw check bits and the syndrome prior to data correction; and a data correction circuit configured to receive the raw data, the raw check bits, and the syndrome from the buffer and correct the raw data with the syndrome.
1 . A hardware-implemented pipeline for a set-associative snoop filter, the pipeline comprising:
a syndrome generator circuit configured to receive a way entry including raw data and raw check bits, and generate a syndrome from the raw data and the raw check bits;
a buffer configured to store the raw data, the raw check bits and the syndrome prior to data correction; and
a data correction circuit configured to receive the raw data, the raw check bits, and the syndrome from the buffer and correct the raw data with the syndrome.
2 . The pipeline of claim 1 , wherein the buffer includes a set of flip-flops.
3 . The pipeline of claim 1 , wherein the raw check bits include a raw Error Correction Code (ECC); and wherein the syndrome generator circuit is configured to generate each syndrome bit by selecting an ECC bit, and performing an exclusive-OR of the selected ECC bit with a selected set of bits of the raw data.
4 . The pipeline of claim 3 , wherein the syndrome generator is implemented with gates that are fast enough to generate the syndrome within a single clock cycle.
5 . The pipeline of claim 3 , further comprising an error detection circuit operable in parallel with the data correction circuit.
6 . The pipeline of claim 5 , wherein the error detection circuit is configured to use the syndrome and a parity bit of the raw ECC to determine whether the raw data has a single bit error or a double bit error.
7 . The pipeline of claim 5 , wherein the syndrome generator circuit is configured to receive a way entry from memory; and wherein the memory and the buffer are configured with clock inputs such that:
the memory is read at clock cycle N and outputs the way entry at clock cycle N+1;
the syndrome is calculated, and the syndrome and the raw data and the raw ECC are captured by the buffer during clock cycle N+1; and
at clock cycle N+2, the data correction circuit corrects the raw data with the syndrome and, in parallel, the error detection circuit uses an ECC parity bit and the syndrome to determine whether the raw data has a single bit error or a double bit error.
8 . A cache coherent interconnect for an electronic system, the cache coherent interconnect comprising:
an interconnector;
a system directory for maintaining cache coherence of the interconnector, the system directory including memory for storing a plurality of snoop filter way entries; and
a plurality of pipelines for performing error correction on way entries from the memory, wherein each pipeline includes:
a syndrome generator circuit configured to receive a way entry including raw data and raw check bits, and generate a syndrome from the raw data and the raw check bits;
a buffer configured to store the raw data, the raw check bits and the syndrome prior to data correction; and
a data correction circuit configured to receive the raw data, the raw check bits, and the syndrome from the buffer and correct the raw data with the syndrome.
9 . The interconnect of claim 8 , wherein the raw check bits include a raw Error Correction Code (ECC); and wherein the syndrome generator circuit of each pipeline is configured to generate each syndrome bit by selecting an ECC bit, and performing an exclusive-OR of the selected ECC bit with a selected set of bits of the raw data.
10 . The interconnect of claim 9 , wherein the syndrome generator of each pipeline is implemented with gates that are fast enough to generate the syndrome within a single clock cycle.
11 . The interconnect of claim 9 , wherein each pipeline further includes an error detection circuit operable in parallel with a data correction circuit.
12 . The interconnect of claim 11 , wherein the error detection circuit of each pipeline is configured to use the syndrome and a parity bit of the raw ECC to determine whether the raw data has a single bit error or a double bit error.
13 . The interconnect of claim 12 , wherein the system directory includes timing circuitry for the snoop filters, wherein:
the memory is read at clock cycle N and outputs a way entry at clock cycle N+1;
the syndrome is calculated, and the syndrome and the raw data and the raw ECC are captured by the buffer during clock cycle N+1; and
at clock cycle N+2, the data correction circuit corrects the raw data with the syndrome and, in parallel, the error detection circuit uses an ECC parity bit and the syndrome to determine whether the raw data has a single bit error or a double bit error.
14 . The interconnect of claim 12 , wherein the system directory further includes circuits configured to perform owner/sharer computations on way entries provided by the pipelines.
15 . The interconnect of claim 14 , the system directory further includes:
a circuit configured to aggregate results of the owner/sharer computations and issue a response if there is a tag hit; and
a circuit configured to issue a recall transaction if there are no tag hits, if an allocation into a home snoop filter is wanted, and if room for the allocation will be made by evicting a way entry in the home snoop filter.
16 . The interconnect of claim 8 , wherein the cache coherent interconnect is a network-on-chip (NoC) and the interconnector includes a transport interconnect.
17 . The interconnect of claim 16 , wherein the NoC further includes last level cache with caching agent, and wherein the caching agent is connected to the transport interconnect.
18 . An electronic system comprising:
a plurality of caching agents; and
a cache-coherent interconnect including a system directory and an interconnect,
wherein the caching agents are configured to communicate with the system directory via the interconnect,
wherein the system directory includes a plurality of snoop filters, each snoop filter including a plurality of way entries,
wherein the system directory further includes a plurality of pipelines, each pipeline associated with one of the way entries and performing data correction on the associated way entry; and
wherein each pipeline includes:
a syndrome generator circuit configured to receive a corresponding way entry, and generate a syndrome from raw data and raw check bits in the corresponding way entry;
a buffer configured to store the raw data, the raw check bits and the syndrome prior to data correction; and
a data correction circuit configured to receive the raw data, the raw check bits, and the syndrome from the buffer and correct the raw data with the syndrome.
19 . The system of claim 18 , wherein:
the raw check bits of each way entry include a raw Error Correction Code (ECC);
the syndrome generator circuit of each pipeline is configured to generate each syndrome bit by selecting an ECC bit, and performing an exclusive-OR of the selected ECC bit with a selected set of bits of the raw data; and
each pipeline further includes an error detection circuit operable in parallel with the data correction circuit and configured to use the syndrome and a parity bit of the raw ECC to determine whether the raw data has a single bit error or a double bit error.
20 . The system of claim 18 , wherein the electronic system is a system-on-chip (SoC) including a cache-coherent network-on-chip (NoC) and wherein the NoC includes the system directory.