Optimizing SMMU cache invalidation
A system is provided for an improved cached STE invalidation. To track which STEs are updated, a memory is provided with a bitmap. Software identifies which STE are updated through the bitmap. Due to the update of the stored STE(s), corresponding STEs in a cache are stale. The software invalidates only the corresponding cached STEs as identified through the bitmap as opposed to invalidating all the cached STEs.
1 . A method of invalidating stream table entries (STEs), comprising:
caching STEs from a plurality of stored STEs stored in a memory into a cache so that the cache stores a plurality of cached STEs;
initializing a bitmap in the memory, wherein the bitmap includes a bit for each stored STE in the plurality of stored STEs so that each bit in the bitmap has a first binary value;
updating an at least one stored STE from the plurality of stored STEs to provide an at least one updated STE;
changing a binary value of each bit in the bitmap corresponding to the at least one updated STE so that the bitmap includes an at least one changed bit having a second binary value;
issuing a command to invalidate the plurality of cached STEs in response to the updating of the at least one stored STE;
identifying each cached STE in the plurality of cached STEs that corresponds to the at least one changed bit to provide an at least one identified STE; and
invalidating only the at least one identified STE in the plurality of cached STEs in response to the command to invalidate the plurality of cached STEs, wherein a remainder of the plurality of the cached STEs that does not include the at least one identified STE is not invalidated.
2 . The method of claim 1 , wherein issuing the command to invalidate the plurality of cached STEs comprises issuing a CMD_CFGI_ALL command.
3 . The method of claim 1 , wherein issuing the command to invalidate the plurality of cached STEs comprises issuing a CMD_CFGI_STE_RANGE(N) command, wherein N is an integer number of stored STEs in the plurality of stored STEs.
4 . The method of claim 1 , further comprising:
writing the plurality of stored STEs to the memory prior to caching the plurality of cached STEs.
5 . The method of claim 1 , wherein caching the plurality of cached STEs into the cache comprises caching the plurality of cached STEs into a processor element cache.
6 . The method of claim 1 , further comprising:
invalidating a configuration from a translation control unit (TCU) cache for a system memory management unit (SMMU) responsive to the command to invalidate the plurality of cached STEs.
7 . The method of claim 6 , further comprising:
writing a starting address of the bitmap to a first register in the SMMU.
8 . The method of claim 7 , further comprising:
writing a size of the bitmap to a second register in the SMMU.
9 . The method of claim 8 , further comprising:
retrieving the starting address from the first register and retrieving the size of the bitmap from the second register; and
accessing the bitmap responsive to the starting address and size of the bitmap to identify the at least one changed bit.
10 . The method of claim 1 , wherein initializing the bitmap comprises resetting each bit in the bitmap, and wherein changing the binary value of each bit in the bitmap corresponding to the at least one stored STE comprises setting the at least one changed bit.
11 . The method of claim 1 , wherein the memory comprises a double data rate (DDR) dynamic random-access memory (DRAM).
12 . A system for invalidating stream table entries (STEs), comprising:
a memory configured to store a plurality of stored STEs;
a cache configured to cache a plurality of cached STEs from the plurality of stored STEs;
an at least one processor configured to:
initialize a bitmap in the memory, wherein the bitmap includes a bit for each stored STE in the plurality of stored STEs so that each bit in the bitmap has a first binary value;
update an at least one stored STE from the plurality of stored STEs to provide an at least one updated STE;
change a binary value of each bit in the bitmap corresponding to the at least one stored STE so that the bitmap includes an at least one changed bit having a second binary value; and
issue a command to invalidate the plurality of cached STEs in response to the update of the at least one stored STE; and
a driver for a system memory management unit (SMMU) configured to:
identify each cached STE in the plurality of cached STEs that corresponds to the at least one changed bit to provide an at least one identified STE; and
invalidate only the at least one identified STE in the plurality of cached STEs in response to the command to invalidate the plurality of cached STEs, wherein a remainder of the plurality of the cached STEs that does not include the at least one identified STE is not invalidated.
13 . The system of claim 12 , wherein the at least one processor is configured to issue a CMD_CFGI_ALL command to invalidate the plurality of cached STEs.
14 . The system of claim 12 , wherein the at least one processor is configured to issue a CMD_CFGI_STE_RANGE(N) command to invalidate the plurality of cached STEs, wherein N is an integer number of stored STEs in the plurality of stored STEs.
15 . The system of claim 12 , wherein the at least one processor is further configured to:
write the plurality of stored STEs to the memory prior to a caching of the plurality of cached STEs.
16 . The system of claim 12 , wherein the cache comprises a processor element cache.
17 . The system of claim 12 , wherein the memory comprises a DDR DRAM.
18 . A system for invalidating stream table entries (STEs), comprising:
a DDR memory configured to store a plurality of stored STEs and including means for flagging at least one stored STE in the plurality of stored STEs as being an at least one updated STE;
an at least one processor configured to:
update an at least one stored STE from the plurality of stored STEs to provide an at least one updated STE; and
issue a command to invalidate a plurality of cached STEs stored in a cache in response to the update of the at least one stored STE; and
a driver for a system memory management unit (SMMU) configured to:
access the means to identify each cached STE in the plurality of cached STEs that corresponds to the at least one updated STE to provide an at least one identified STE; and
invalidate only the at least one identified STE in the plurality of cached STEs in response to the command to invalidate the plurality of cached STEs, wherein a remainder of the plurality of the cached STEs that does not include the at least one identified STE is not invalidated.
19 . The system of claim 18 , wherein the DDR memory comprises a DDR DRAM.
20 . The system of claim 18 , wherein the cache comprises a plurality of processor element caches.