Systems, methods, and apparatus for interference avoidance in memory systems

1 . A method comprising:

allocating a first memory page from a first type of pseudo-channel based on a first access pattern for the first memory page, wherein the first type of pseudo-channel is configured for an interleaving operation and the first access pattern is sequential;

allocating a second memory page from a second type of pseudo-channel based on a second access pattern for the second memory page, wherein the second type of pseudo-channel is configured for a partitioned operation and the second access pattern is non-sequential;

monitoring an access of the second memory page;

detecting, based on the monitoring, interference associated with the second memory page; and

allocating, based on the detecting, a third memory page from the first type of pseudo-channel based on a third access pattern for the third memory page, wherein the third access pattern is non-sequential.

2 . The method of claim 1 , wherein the first memory page is allocated based on an access pattern indication.

3 . The method of claim 2 , wherein:

the first memory page is allocated based on a request received from a user; and

the access pattern indication is received from the user.

4 . The method of claim 1 , wherein:

the interference comprises command bus contention.

5 . The method of claim 1 , wherein:

the first type of pseudo-channel is mapped to a first portion of an address space; and

the second type of pseudo-channel is mapped to a second portion of the address space.

6 . The method of claim 1 , wherein the interleaving operation comprises channel interleaving.

7 . The method of claim 1 , wherein the interleaving operation comprises bank interleaving.

8 . The method of claim 1 , wherein:

the first memory page is allocated from a first block of memory associated with a first channel; and

the third memory page is allocated from a second block of memory associated with a second channel.

9 . A memory system comprising:

a monitoring circuit configured to detect interference associated with a first memory page;

at least one processing circuit configured to:

allocate the first memory page from a first type of pseudo-channel based on a first access pattern for the first memory page, wherein the first type of pseudo-channel is configured for interleaving operation and the first access pattern is sequential;

allocate a second memory page from a second type of pseudo-channel based on a second access pattern for the second memory page, wherein the second type of pseudo-channel is configured for partitioned operation and the second access pattern is non-sequential; and

allocate, based on the interference, a third memory page from the first type of pseudo-channel based on a third access pattern for the third memory page, wherein the third access pattern is non-sequential.

10 . The memory system of claim 9 , wherein the at least one processing circuit is configured to:

receive an access pattern indication; and

allocate the first memory page based on the access pattern indication.

11 . The memory system of claim 9 , wherein:

the at least one processing circuit is configured to allocate the first memory page using a first memory mapping scheme; and

the at least one processing circuit is configured to allocate, based on the interference, the third memory page using a second memory mapping scheme.

12 . A memory system comprising:

a monitoring circuit configured to detect interference associated with a first memory page; and

at least one processing circuit configured to:

allocate the first memory page from a first portion of an address space based on a first access pattern for the first memory page, wherein the first portion of the address space is configured for a first interleaving scheme;

allocate a second memory page from a second portion of the address space based on a second access pattern for the second memory page, wherein the second portion of the address space is configured for a second interleaving scheme; and

configure, based on the interference, the first portion of the address space for the second interleaving scheme.

13 . The memory system of claim 12 , wherein:

the first access pattern comprises a sequential access pattern; and

the second access pattern comprises a non-sequential access pattern.

14 . The memory system of claim 12 , wherein:

the first memory page is allocated from a first pseudo-channel mapped to the first portion of the address space; and

the second memory page is allocated from a second pseudo-channel mapped to the second portion of the address space.

15 . The memory system of claim 12 , wherein the interference comprises command bus contention.