Data storage method and system, storage access configuration method, and related device

1 . A system, comprising:

a host configured to:

establish, through a bus, a first communication connection; and

send, through the first communication connection and using memory semantic operations, first data that the host requests to write into a first address of a first memory space, wherein the first memory space supports memory semantic access, and wherein the memory semantic operations comprise byte-level addressing operations to access the first memory space using load and store operations directed to byte-addressable physical addresses;

a storage node comprising a second memory space and configured to establish, through a network, a second communication connection; and

an adapter card configured to:

provide the first memory space for the host, wherein the first memory space is mapped from a capacity of the second memory space of the storage node and is configured to support memory semantic access operations from the host;

receive, through the first communication connection and from the host, the first data, wherein the first data is received as the memory semantic operations comprising the byte-level addressing operations;

write, through the second communication connection, the first data into the second memory space by converting the memory semantic access operations received from the host to remote direct memory access (RDMA) network protocol operations for transmitting the first data to the storage node; and

store a first correspondence between a physical address of the second memory space and the first address, wherein the first correspondence maps byte-level addresses from the memory semantic access operations to physical addresses of the second memory space.

2 . The system of claim 1 , wherein the host comprises a second correspondence between the first address and a virtual memory address of an application.

3 . The system of claim 2 , wherein the adapter card is further configured to write, into a second address of the second memory space and in an RDMA manner, the first data by converting the memory semantic operations to RDMA network protocol operations, and wherein the first address in the first correspondence corresponds to the second address.

4 . The system of claim 3 , wherein the adapter card further comprises a cache, wherein the first correspondence further comprises a third correspondence between the first address and the cache, and wherein the adapter card stores data received as byte-level addressing operations from the host into the cache.

5 . The system of claim 4 , wherein the adapter card is further configured to:

write, into a cache address of the cache, the first data;

update the first address in the first correspondence to correspond to the cache address;

write, in the RDMA manner, the first data into the second address of the second memory space when an amount of second data in the cache reaches a threshold; and

update the first address in the first correspondence to correspond to the second address.

6 . The system of claim 5 , wherein the host is further configured to send, to the adapter card, a first read request for the first address, and wherein the adapter card is further configured to process, based on the cache address, the first read request when a third address corresponding to the first address is the cache address.

7 . The system of claim 6 , wherein when the third address is the second address, the adapter card is further configured to:

return, to the host, a cache miss message;

send, to the storage node, a second read request for the second address;

receive, in response to the second read request and from the storage node, the first data;

store, into the cache, the first data; and

update the first correspondence.

8 . The system of claim 7 , wherein the host further comprises a retry queue comprising a missed data read request and context information of the missed data read request, and wherein the host is further configured to use the retry queue to resend, based on the context information and to the adapter card, the missed data read request.

9 . The system of claim 1 , wherein the second memory space is a non-volatile dual in-line memory module (NVDIMM).

10 . The system of claim 1 , wherein the bus comprises a Peripheral Component Interconnect Express (PCIe) bus.

11 . The system of claim 1 , wherein the adapter card further comprises a cache, and wherein the adapter card is further configured to:

write the first data into a cache address of the cache;

update the first correspondence to map the first address to the cache address;

write the first data into a second address of the second memory space using the RDMA network protocol operations when an amount of data in the cache reaches a threshold; and

update the first correspondence to map the first address to the second address.

12 . An adapter card, comprising:

a memory configured to store instructions; and

one or more processors coupled to the memory and configured to execute the instructions to:

establish, through a bus, a first communication connection with a host;

provide, for the host, first memory space that supports memory semantic access, wherein the first memory space is mapped from a capacity of a second memory space of a storage node and is configured to support memory semantic access operations from the host;

receive, through the first communication connection and from the host, first data that the host requests to write into a first address of the first memory space, wherein the first data is received as memory semantic operations comprising byte-level addressing operations;

establish, through a network, a second communication connection with the storage node;

write, through the second communication connection and into the second memory space of the storage node, the first data by converting the memory semantic access operations received from the host to remote direct memory access (RDMA) network protocol operations for transmitting the first data to the storage node; and

store a first correspondence between a physical address of the second memory space and the first address, wherein the first correspondence maps byte-level addresses from the memory semantic access operations to physical addresses of the second memory space.

13 . The adapter card of claim 12 , wherein the one or more processors are further configured to execute the instructions to write, into a second address of the second memory space and in an RDMA manner, the first data by converting the memory semantic operations to RMDA network protocol operations, and wherein the first address in the first correspondence corresponds to the second address.

14 . The adapter card of claim 13 , wherein the adapter card further comprises a cache, wherein the first correspondence further comprises a third correspondence between the first address and the cache, and wherein the adapter card stores data received as byte-level addressing operations from the host into the cache.

15 . The adapter card of claim 14 , wherein the one or more processors are further configured to execute the instructions to:

write, into a cache address of the cache, the first data;

update the first address in the first correspondence to correspond to the cache address;

write, in the RDMA manner, the first data into the second address of the second memory space when an amount of second data in the cache reaches a threshold; and

update the first address in the first correspondence to correspond to the second address.

16 . The adapter card of claim 15 , wherein the one or more processors are further configured to execute the instructions to:

receive, from the host, a first read request for the first address; and

process, based on the cache address, the first read request when a third address corresponding to the first address is the cache address.

17 . The adapter card of claim 16 , wherein when the third address is the second address, the one or more processors are further configured to execute the instructions to:

return, to the host, a cache miss message;

send, to the storage node, a second read request for the second address;

receive, in response to the second read request and from the storage node, the first data;

store, into the cache, the first data; and

update the first correspondence.

18 . The adapter card of claim 12 , wherein the second memory space is a non-volatile dual in-line memory module (NVDIMM).

19 . The adapter card of claim 12 , wherein the bus comprises one or more of a Compute Express Link (CXL) bus or a generation Z (GenZ) bus.

20 . A method, comprising:

establishing, through a bus, a first communication connection with a host;

providing, for the host, a first memory space that supports memory semantic access, wherein the first memory space is mapped from a capacity of a second memory space of a storage node and is configured to support memory semantic access operations from the host;

receiving, through the first communication connection and from the host, first data that the host requests to write into a first address of the first memory space, wherein the first data is received as memory semantic operations comprising byte-level addressing operations;

establishing, through a network, a second communication connection with the storage node;

writing, through the second communication connection and into the second memory space of the storage node, the first data by converting the memory semantic access operations received from the host to remote direct memory access (RDMA) network protocol operations for transmitting the first data to the storage node; and

storing a first correspondence between a physical address of the second memory space and the first address, wherein the first correspondence maps byte-level addresses from the memory semantic access operations to physical addresses of the second memory space.