System, method, device, processor, and storage medium thereof for implementing large-scale FIFO data processing based on DDR

1 . A system for implementing large-scale FIFO data processing based on DDR, the system comprising:

an ingress asynchronous clock domain FIFO, with independent write clocks and read clocks, independently setting a write data bit width and a read data bit width for data writing operations;

a burst read and write data block chain table, connected with the ingress asynchronous clock domain FIFO, for writing a data block chaining table and reading the data block chaining table by setting of the data bit width and the data block length;

a DDR4 AXI interface, connected with the burst read and write data block chain table, for interacting with a flow control state machine and the burst read and write data block chain table;

an egress asynchronous clock domain FIFO, connected with the burst read and write data block chain table, with independent write clocks and read clocks, setting the write data bit width and read data bit width settings independently for data output operations; and

the flow control state machine, connected with the ingress asynchronous clock domain FIFO, the DDR4 AXI interface, and the egress asynchronous clock domain FIFO, used for data flow control to monitor writes and reads of data streams to the ingress asynchronous clock domain FIFO, the DDR4 AXI interface and the egress asynchronous clock domain FIFO,

wherein the burst read and write data block chain table includes a counting monitoring variable to detect the number of operations of the ingress asynchronous clock domain FIFO and the egress asynchronous clock domain FIFO, and counts and monitors data writing and reading out of the DDR4 AXI interface.

2 . The system for implementing large-scale FIFO data processing based on DDR according to claim 1 , wherein the burst read and write data block chain table carries out a data flow coherent operation under the control of a flow control state machine according to read and write signal changes of the ingress asynchronous clock domain FIFO and the egress asynchronous clock domain FIFO.

3 . The system for implementing large-scale FIFO data processing based on DDR according to claim 1 , wherein operating modes of the system described are a transparency transport mode and a transit transport mode, said transparency transport mode means that in a case of a short data duration and not exceeding the FIFO depths of the ingress asynchronous clock domain FIFO and the egress asynchronous clock domain FIFO, data streams are directly passed through the ingress asynchronous clock domain FIFO and the egress asynchronous clock domain FIFO for the purpose of data transmission; the transit transport mode described refers to the transit of the data streams through a buffer space of the DDR4 AXI interface in the event that a continuous data duration is long and exceeds the threshold value ingress asynchronous clock domain FIFO and egress asynchronous clock-domain FIFO of FIFO depth.

4 . The system for implementing large-scale FIFO data processing based on DDR according to claim 1 , wherein said system has a read bandwidth of the egress asynchronous clock domain FIFO in a transparency transport mode that is greater than the write bandwidth of the ingress asynchronous clock domain FIFO.

5 . A method of implementing large-scale FIFO data processing based on DDR using the system of claim 1 , wherein the method comprises the following steps:

(1) power-on reset, ingress asynchronous clock domain FIFO writes data;

(2) determine whether the ingress asynchronous clock domain FIFO written data is greater than a threshold value, if so, a working mode turns to a transit transport mode, turning on DDR4 access and using DDR4 as cache space for read and write operations; otherwise, the working mode turns to a transparency transport mode.

6 . The method for implementing large-scale FIFO data processing based on DDR according to claim 5 , wherein the method comprises the step of implementing a FIFO read and write operation through the transit transport mode, specifically comprises the following processing:

(1-1) the DDR4 AXI interface performs burst accesses using a data block as a unit of operation to obtain monitoring variables for a data block count value and a number of ingress FIFO data reads;

(1-2) the ingress asynchronous clock domain FIFO acquires a full length block of data;

(1-3) if a write bus of the DDR4 AXI interface is in a READY state, a write enable is issued and a internal count value is updated; if a read bus of the DDR4 AXI interface is in the READY state, a read enable is issued, summarized data is passed to the egress asynchronous clock domain FIFO, and the internal count value is updated.

7 . The method for implementing large-scale FIFO data processing based on DDR according to claim 5 , wherein the method comprises the step of implementing a FIFO read and write operation through the transparency transport mode, specifically comprises the following processing:

(2-1) power-on reset, an empty signal of the ingress asynchronous clock domain FIFO is high and the full signal of the egress asynchronous clock domain FIFO is low;

(2-2) write data, the empty signal of the ingress asynchronous clock domain FIFO is low, and according to a timing jump formula, a read enable of the ingress asynchronous clock domain FIFO is obtained as high;

(2-3) counts a number of data reads from the ingress asynchronous clock domain FIFO, and if the number of data reads exceeds the threshold value, a mode signal automatically jumps to the transit transport mode; otherwise, it continues to the transparency transport mode, and continues with step (2-4);

(2-4) data is read from the ingress asynchronous clock domain FIFO and written to the egress asynchronous clock domain FIFO, and the egress asynchronous clock domain FIFO write enable signal performs a timing jump according to equation;

(2-5) determine whether the ingress asynchronous clock domain FIFO is read empty or the egress asynchronous clock domain FIFO is written full; if so, no further operation is performed on the ingress asynchronous clock domain FIFO and the step is exited; otherwise, read and write operations continue to be performed on the ingress asynchronous clock domain FIFO.

8 . The method for implementing large-scale FIFO data processing based on DDR according to claim 7 , wherein an effective signal of the ingress asynchronous clock domain FIFO in said step (2-4) is delayed by one clock according to a state of the read enable signal of the ingress asynchronous clock domain FIFO and an acquired signal of the ingress asynchronous clock domain FIFO before jumping.

9 . A device for implementing large-scale FIFO data processing based on DDR, wherein the device comprises:

processor, configured to execute computer-executable instructions;

memory, storing said computer-executable instructions, when said computer-executable instructions are executed by said processor, various steps for realizing the method of implementing large-scale FIFO data processing based on DDR as claimed in claim 5 .

10 . A processor for implementing large-scale FIFO data processing based on DDR, wherein a processor is configured to execute computer-executable instructions, and when said processor executes computer-executable instructions, the method of implementing large-scale FIFO data processing based on DDR as claimed in claim 5 is performed.

11 . A non-transitory computer-readable storage medium having a computer program stored on it, wherein the computer program may be executed by a processor to implement the various steps for realizing the method of implementing large-scale FIFO data processing based on DDR as claimed in claim 5 .

12 . The system for implementing large-scale FIFO data processing based on DDR according to claim 1 , wherein the flow control state machine uses a Round-Robin scheduling algorithm to achieve Round-Robin scheduling policy for data stream writes and reads to ensure data coherence and improve DDR4 interface bandwidth utilization.