Processor platform, circuit board, and server

1 . A processor platform, wherein the processor platform comprises one or more processors;

any one of the one or more processors has at least one ultra-path interconnecting port;

the ultra-path interconnecting ports of different instances of the one or more processors correspond one to one;

the ultra-path interconnecting ports of different instances of the one or more processors are connected correspondingly; and

the one or more processors include at least one port expanding processor, and the port expanding processor has an expansible data port;

in response to the processor platform comprising at least two processors, the processor platform further comprises one or more expansible Open Computer Project (OCP) links;

each of the one or more expansible OCP links comprises a first processor, a first connector and a second connector;

the first connector has a first first-connector port set and a second first-connector port set, and the second connector has a second-connector port set;

the first processor has a first first-processor port set;

the first first-processor port set corresponds to the first first-connector port set;

the ports in the first first-processor port set are connected correspondingly to the ports in the first first-connector port set; and

the ports in the second first-connector port set are connected correspondingly to the ports in the second-connector port set;

wherein the processor platform further comprises a third connector, and the third connector has a third-connector port set;

the first processor further has a second first-processor port set;

port serial-numbers of channels in the third-connector port set correspond to the port serial-numbers of the channels in the second-connector port set, and port serial-numbers of channels in the second first-processor port set correspond to the port serial-numbers of the channels in the third-connector port set;

the ports in the second-connector port set are connected correspondingly to the ports in the third-connector port set according to the port serial-numbers of the channels; and

the ports in the third-connector port set are connected correspondingly to the ports in the second first-processor port set according to the port serial-numbers of the channels;

wherein the processor platform further comprises a second processor and a fourth connector;

the second processor has a second second-processor port set;

the fourth connector has a fourth-connector port set;

port serial-numbers of channels in the fourth-connector port set correspond to the port serial-numbers of the channels in the second-connector port set, and port serial-numbers of channels in the second second-processor port set correspond to the port serial-numbers of the channels in the fourth-connector port set;

the ports in the second-connector port set are connected correspondingly to the ports in the fourth-connector port set according to the port serial-numbers of the channels, to replace the ports in the second-connector port set to be connected correspondingly to the ports in the third-connector port set; and

the ports in the fourth-connector port set are connected correspondingly to the ports in the second second-processor port set according to the port serial-numbers of the channels.

2 . The processor platform according to claim 1 , wherein the processor platform further comprises a complex programmable logic device;

the complex programmable logic device has a first complex-programmable-logic-device port and a second complex-programmable-logic-device port;

the second connector further has a first second-connector port and a second second-connector port;

the first second-connector port is connected to the first complex-programmable-logic-device port, to indicate whether the second connector is connected to the third connector or the fourth connector; and

the second second-connector port is connected to the second complex-programmable-logic-device port, to indicate that the second connector is connected to the third connector or that the second connector is connected to the fourth connector.

3 . The processor platform according to claim 1 , wherein the expansible data port has a plurality of Peripheral Component Interconnect Express (PCIe) channel pairs;

the PCIe channel pairs of a first quantity are connected to a corresponding port of a baseboard management controller;

the PCIe channel pairs of a second quantity are connected to a Universal Serial Bus (USB) interface; and

the PCIe channel pairs of a third quantity are connected to a Serial Advanced Technology Attachment (SATA) interface.

4 . The processor platform according to claim 3 , wherein a link connecting the PCIe channel pairs of the second quantity and the USB interface comprises a USB controller; and

the PCIe channel pairs of the second quantity are connected to the USB interface by the USB controller.

5 . The processor platform according to claim 4 , wherein the USB interface comprises at least one of an SCM (single chip microcomputer) USB interface and an MB USB interface.

6 . The processor platform according to claim 4 , wherein the USB interface is a USB2.0 interface and/or a USB3.0 interface.

7 . The processor platform according to claim 3 , wherein a link connecting the PCIe channel pairs of the third quantity and the SATA interface comprises an SATA converter; and

the PCIe channel pairs of the third quantity are connected to the SATA interface by the SATA converter.

8 . The processor platform according to claim 3 , wherein the port expanding processor further comprises a plurality of first transmitting ports; and

each of the first transmitting ports comprises 4 instances of the PCIe channel pairs.

9 . The processor platform according to claim 3 , wherein the port expanding processor further comprises a second transmitting port; and

the second transmitting port comprises 8 instances of the PCIe channel pairs.

10 . The processor platform according to claim 2 , wherein the first second-connector port is configured for transmitting a position signal;

the second second-connector port is configured for transmitting a type signal;

the first complex-programmable-logic-device port is configured for receiving the position signal; and

the second complex-programmable-logic-device port is configured for receiving the type signal.

11 . The processor platform according to claim 10 , wherein in response to the second connector being connected to the third connector or the fourth connector, the position signal is a low level; and

in response to the third connector being connected to the second connector, the type signal is a high level.

12 . The processor platform according to claim 1 , wherein the port expanding processor is a processor that is not integrated with a south-bridge module.

13 . The processor platform according to claim 1 , wherein the ultra-path interconnecting ports are configured for transmitting communication data among the processors.

14 . The processor platform according to claim 1 , wherein the expansible OCP link has a single-port Single-Host x8 interface.

15 . A circuit board, wherein the circuit board comprises a processor platform;

wherein the processor platform comprises one or more processors;

any one of the one or more processors has at least one ultra-path interconnecting port;

the ultra-path interconnecting ports of different instances of the one or more processors correspond one to one;

the ultra-path interconnecting ports of different instances of the one or more processors are connected correspondingly; and

the one or more processors include at least one port expanding processor, and the port expanding processor has an expansible data port;

in response to the processor platform comprising at least two processors, the processor platform further comprises one or more expansible Open Computer Project (OCP) links;

each of the one or more expansible OCP links comprises a first processor, a first connector and a second connector;

the first connector has a first first-connector port set and a second first-connector port set, and the second connector has a second-connector port set;

the first processor has a first first-processor port set;

the first first-processor port set corresponds to the first first-connector port set;

the ports in the first first-processor port set are connected correspondingly to the ports in the first first-connector port set; and

the ports in the second first-connector port set are connected correspondingly to the ports in the second-connector port set;

wherein the processor platform further comprises a third connector, and the third connector has a third-connector port set;

the first processor further has a second first-processor port set;

port serial-numbers of channels in the third-connector port set correspond to the port serial-numbers of the channels in the second-connector port set, and port serial-numbers of channels in the second first-processor port set correspond to the port serial-numbers of the channels in the third-connector port set;

the ports in the second-connector port set are connected correspondingly to the ports in the third-connector port set according to the port serial-numbers of the channels; and

the ports in the third-connector port set are connected correspondingly to the ports in the second first-processor port set according to the port serial-numbers of the channels;

wherein the processor platform further comprises a second processor and a fourth connector;

the second processor has a second second-processor port set;

the fourth connector has a fourth-connector port set;

port serial-numbers of channels in the fourth-connector port set correspond to the port serial-numbers of the channels in the second-connector port set, and port serial-numbers of channels in the second second-processor port set correspond to the port serial-numbers of the channels in the fourth-connector port set;

the ports in the second-connector port set are connected correspondingly to the ports in the fourth-connector port set according to the port serial-numbers of the channels, to replace the ports in the second-connector port set to be connected correspondingly to the ports in the third-connector port set; and

the ports in the fourth-connector port set are connected correspondingly to the ports in the second second-processor port set according to the port serial-numbers of the channels.

16 . A server, wherein the server comprises a circuit board,

wherein the circuit board comprises a processor platform;

wherein the processor platform comprises one or more processors;

any one of the one or more processors has at least one ultra-path interconnecting port;

the ultra-path interconnecting ports of different instances of the one or more processors correspond one to one;

the ultra-path interconnecting ports of different instances of the one or more processors are connected correspondingly; and

the one or more processors include at least one port expanding processor, and the port expanding processor has an expansible data port;

in response to the processor platform comprising at least two processors, the processor platform further comprises one or more expansible Open Computer Project (OCP) links;

each of the one or more expansible OCP links comprises a first processor, a first connector and a second connector;

the first connector has a first first-connector port set and a second first-connector port set, and the second connector has a second-connector port set;

the first processor has a first first-processor port set;

the first first-processor port set corresponds to the first first-connector port set;

the ports in the first first-processor port set are connected correspondingly to the ports in the first first-connector port set; and

the ports in the second first-connector port set are connected correspondingly to the ports in the second-connector port set;

wherein the processor platform further comprises a third connector, and the third connector has a third-connector port set;

the first processor further has a second first-processor port set;

port serial-numbers of channels in the third-connector port set correspond to the port serial-numbers of the channels in the second-connector port set, and port serial-numbers of channels in the second first-processor port set correspond to the port serial-numbers of the channels in the third-connector port set;

the ports in the second-connector port set are connected correspondingly to the ports in the third-connector port set according to the port serial-numbers of the channels; and

the ports in the third-connector port set are connected correspondingly to the ports in the second first-processor port set according to the port serial-numbers of the channels;

wherein the processor platform further comprises a second processor and a fourth connector;

the second processor has a second second-processor port set;

the fourth connector has a fourth-connector port set;

port serial-numbers of channels in the fourth-connector port set correspond to the port serial-numbers of the channels in the second-connector port set, and port serial-numbers of channels in the second second-processor port set correspond to the port serial-numbers of the channels in the fourth-connector port set;

the ports in the second-connector port set are connected correspondingly to the ports in the fourth-connector port set according to the port serial-numbers of the channels, to replace the ports in the second-connector port set to be connected correspondingly to the ports in the third-connector port set; and

the ports in the fourth-connector port set are connected correspondingly to the ports in the second second-processor port set according to the port serial-numbers of the channels.

17 . The processor platform according to claim 1 , wherein the expansible OCP link has a single-port Single-Host x16 interface.

18 . The processor platform according to claim 4 , wherein a signal of the USB controller is Renesas UPD720201, and each of the PCIe channel pairs of the second quantity is connected to the USB interface by one Renesas UPD720201 module.