System on chip

1 . A system on chip comprising:

a bus including a data channel through which data is transmitted in at least one direction; and

a master interface configured to

receive first data,

perform a bit operation on the first data and on second data output by the master interface and corresponding to a clock cycle before a clock cycle of the first data,

determine an encoding operation for the first data based on a result of the bit operation;

perform the encoding operation on the first data, to obtain encoded data; and

provide the encoded data and a transformation signal indicating the encoding operation to the data channel, wherein a first value of the transformation signal indicates a circular shift operation as the encoding operation.

2 . The system on chip of claim 1 , wherein the encoding operation comprises a maintenance operation, an invert operation, or the circular shift operation.

3 . The system on chip of claim 2 , wherein the transformation signal is 1 bit.

4 . The system on chip of claim 1 , wherein the master interface is configured to provide a second value of the transformation signal indicating an invert operation, and

wherein the first value of the transformation signal and the second value of the transformation signal are the same.

5 . The system on chip of claim 1 , wherein the master interface is configured to provide a second value of the transformation signal indicating an invert operation, and a third value of the transformation signal indicating a maintenance operation, and

wherein the second value of the transformation signal and the third value of the transformation signal are different from each other.

6 . The system on chip of claim 1 , wherein the circular shift operation includes shifting the first data by 2 bit units.

7 . The system on chip of claim 1 , wherein the master interface comprises:

a first bit operator that outputs an XOR result value by performing an XOR bit operation on the first data and the second data; and

a second bit operator that outputs an XNOR result value by performing an XNOR bit operation on (i) first shift data obtained by performing the circular shift operation on the first data, and (ii) the second data.

8 . The system on chip of claim 7 , wherein the master interface comprises:

a first adder configured to output a first sum value by bit counting the XOR result value;

a second adder configured to output a second sum value by bit counting the XNOR result value;

a first comparator configured to output an invert signal based on the first sum value and a number of bits of the first data; and

a second comparator configured to output a shift signal based on the first sum value, the second sum value, and the number of bits of the first data.

9 . The system on chip of claim 8 , wherein the first comparator is configured to output the invert signal based on whether the first sum value is greater than the number of bits of the first data divided by two.

10 . The system on chip of claim 8 , wherein the second comparator is configured to output the shift signal based on whether the second sum value is greater than a difference between the number of bits of the first data and the first sum value.

11 . The system on chip of claim 1 , wherein the master interface comprises a control unit configured to receive an invert signal, a shift signal, and at least a part of the first data,

wherein the invert signal and the shift signal are based on the result of the bit operation.

12 . The system on chip of claim 11 , wherein the control unit is configured to output an invert enable signal for the invert signal and a shift enable signal for the shift signal, and

wherein the master interface is configured to

receive the invert signal, the shift signal, the invert enable signal, and the shift enable signal,

enable the invert signal and the shift signal, and

output the transformation signal.

13 . The system on chip of claim 12 , wherein the control unit is configured to turn off the invert enable signal and the shift enable signal when the first data and the second data are not provided to the data channel in a burst mode.