Method and apparatus with peripheral component interconnect express (PCIe) data transmission

1 . A method with peripheral component interconnect express (PCIe) data transmission, the method comprising:

receiving, at an endpoint (EP), a doorbell (DB) message transmitted from a root complex (RC) via a PCIe connection between the endpoint (EP) and the RC;

based on the DB message, transmitting, by polling of a processor of the EP, a read request message to a direct memory access (DMA) controller of the EP; and

in response to reception of the read request message by the DMA controller, reading, by the DMA controller, data to be transmitted from a memory of the RC and recording read data into a memory of the EP;

stopping the polling transmission of the read request message to the DMA controller by the EP processor responsive to there being no more of the data to be transmitted from the processor of the EP in the memory of the RC; and

flushing, by the processor of the EP data to be transmitted from a second cache of the processor of the EP to the memory of the EP responsive to a data transmission request by the processor of the EP,

wherein, the determining that there is no more of the data to be transmitted from the processor of the EP is based on the read data from the memory of the RC from the processor of the EP comprising a data terminator.

2 . The method of claim 1 , further comprising:

in response to recording the read data into the memory of the EP from the processor of the EP, recording the read data from the memory of the EP after invalidating data in a first cache of the processor of the EP,

wherein the processor of the EP operates in a cacheable mode.

3 . The method of claim 1 , further comprising:

recording the data to be transmitted in the second cache responsive to reception of the data transmission request by the processor of the EP;

recording the data to be transmitted from the DMA controller from the memory of the EP to the memory of the RC,

wherein the processor of the EP operates in a cacheable mode.

4 . The method of claim 3 , further comprising:

after recording the data to be transmitted from the processor of the EP into the second cache, recording a data terminator in the second cache; and

inputting the data terminator from the processor of the EP from the second cache to the memory of the EP.

5 . The method of claim 1 , wherein the reading of the data to be transmitted from the memory of the RC and the recording of the read data in the memory of the EP comprises:

reading a data packet in the memory of the RC in a preset length from the DMA controller.

6 . The method of claim 5 , further comprising:

determining whether a number of data packets read from the processor of the EP is an integer multiple of a preset number;

when the number of data packets read from the processor of the EP is the integer multiple of the preset number, determining whether the preset length is greater than a length of a data packet having a greatest length among the preset number of data packets which are recently read; and

when the preset length is determined that the preset length is greater than a length of the data packet having the greatest length among the preset number of data packets read from the processor the EP, updating the preset length to the greatest length.

7 . The method of claim 5 , further comprising:

determining whether a number of data packets read from the processor of the EP is an integer multiple of a preset number;

when a number of data packets read from the processor of the EP is not the integer multiple of the preset number, determining whether a length of the data packet is greater than the preset length based on data of the read data packet;

when the length of the data packet is determined that the length of the data packet is greater than the preset length in the processor of the EP, updating the preset length to the length of the data packet; and

when the length of the data packet is determined that the length of the data packet is greater than the preset length in the DMA controller, reading the data packet again in the length of the data packet.

8 . A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1 .

9 . A method of peripheral component interconnect express (PCIe) data transmission, the method comprising:

receiving a PCIe message signaled interrupts (MSI) message transmitted by an endpoint (EP) via a PCIe connection to a root complex (RC); and

reading data in a memory of the RC from a processor of the RC by polling performed by the processor of the RC;

stopping polling that causes the reading the data responsive to determining that the data does not exist in the memory of the RC; and

flushing the data to be transmitted from the processor of the RC from the fourth cache to the memory of the RC responsive to a data transmission request by the processor of the EP; and

when a terminator is comprised in data read from the memory of the RC in the processor of the RC, determining that the data to be transmitted does not exist in the memory of the RC,

wherein the data in the memory of the RC is recorded by a direct memory access (DMA) controller of the EP.

10 . The method of claim 9 , further comprising:

in response to reading data of the memory of the RC from the processor of the RC by the polling, recording read data in a third cache after invalidating data in the third cache of the processor of the RC,

wherein the processor of the RC operates in a cacheable mode.

11 . The method of claim 9 , further comprising:

in response to reception of a data transmission request from the processor of the RC, recording data to be transmitted into a fourth cache of the processor of the RC;

and

transmitting a doorbell (DB) message from the processor of the RC to the EP,

wherein the processor of the RC operates in a cacheable mode.

12 . The method of claim 11 , further comprising:

after recording the data to be transmitted from the processor of the RC into the fourth cache, recording a data terminator in the fourth cache and flushing the data terminator from the fourth cache to the memory of the RC.

13 . An endpoint (EP), comprising:

an interface configured to receive a doorbell (DB) message from a root complex (RC) connected to the EP based on peripheral component interconnect express (PCIe);

a processor configured to transmit a read request message to a direct memory access (DMA) controller of the EP by polling; and

the DMA controller configured to read data to be transmitted from a memory of the RC in response to reception of the read request message, and record read data in a memory of the EP,

wherein the processor is further configured to:

stop transmission of the read request message to the DMA controller responsive to determining that the data to be transmitted does not exist in the memory of the RC; and

flushing data to be transmitted from a second cache of the processor of the EP to the memory of the EP responsive to a data transmission request by the processor of the EP, and

wherein, the determining that there is no more of the data to be transmitted from the processor of the EP is based on the read data from the memory of the RO from the processor of the EP comprising a data terminator.

14 . A root complex (RC) comprising:

an interface configured to receive a peripheral component interconnect express (PCIe) message signaled interrupts (MSI) message transmitted by an endpoint (EP) via a PCIe connection; and

a processor configured to:

read data in a memory of the RC by polling;

stop the polling responsive to determining that the data does not exist in the memory of the RC; and

flush data to be transmitted from a second cache of the processor of the EP to the memory of the EP responsive to a data transmission request by the processor of the EP,

wherein, the determining that there is no more of the data to be transmitted from the processor of the EP is based on the read data from the memory of the RC from the processor of the EP comprising a data terminator, and

wherein the data in the memory of the RC is recorded by a direct memory access (DMA) controller of the EP based on the polling.