Physically unclonable function cells with hot carrier injection
Devices including an arrangement of multiple of physically unclonable function (PUF) cells organized to generate a bit pattern, and wherein the PUF cells each includes multiple inverting stages, each inverting stage configured to enable a short circuit between outputs of a pair of inverters to enable accelerated aging of one of the inverters.
1 . A device comprising:
a plurality of physically unclonable function (PUF) cells arranged to generate a bit pattern; and wherein the PUF cells each comprises a plurality of inverting stages; wherein the plurality of inverting stages are arranged into an edge chasing circuit; each inverting stage configured to enable a short circuit between outputs of a pair of inverters to enable accelerated aging of one of the inverters; and wherein a first of the inverting stages is configured to receive an aging value and a second of the inverting stages adjacent to the first of the inverting stages is configured to receive a complement of the aging value.
2 . The PUF cell of claim 1 , wherein the pair of inverters that a particular one of the inverting stages is configured to enable a short circuit between is comprised by the particular one of the inverting stages.
3 . The PUF cell of claim 1 , wherein a first inverter of the pair of inverters is comprised by a first one of the inverting stages and a second inverter of the pair of inverters is comprised by a second one of the inverting stages.
4 . The device of claim 1 , wherein at least some of the inverting stages comprise a diode-clamped inverter (DCI).
5 . The PUF cell of claim 4 , wherein a first inverter of the pair of inverters is a first DCI and a second inverter of the pair of inverters is a second DCI.
6 . The PUF cell of claim 4 , comprising a transmission gate configured to enable a short circuit between an output of a first DCI and an input of a second DCI.
7 . A physically unclonable function (PUF) cell comprising:
an edge chasing arrangement of inverting stages arranged into an edge chasing circuit each comprising a first inverter; and one or more of the inverting stages configured to enable accelerated hot carrier injection (HCI) aging on the first inverter by shorting an output of the first inverter with an output of a second inverter; and wherein a first of the inverting stages is configured to receive an aging value and a second of the inverting stages adjacent to the first of the inverting stages is configured to receive a complement of the aging value.
8 . The PUF cell of claim 7 , wherein the first inverter and the second inverter are comprised by one of the inverting stages.
9 . The PUF cell of claim 7 , wherein the first inverter is comprised by a first one of the inverting stages and the second inverter is comprised by a second one of the inverting stages.
10 . The PUF cell of claim 7 , wherein at least one of the inverting stages comprises a multiplexer configured to output to a parallel arrangement of inverters.
11 . The PUF cell of claim 10 , wherein the parallel arrangement of inverters comprises a first branch comprising an odd number of inverters and a second branch comprising an even number of inverters, and the two branches are merged at an output node of the inverting stage.
12 . The PUF cell of claim 7 , wherein at least one of the inverting stages comprises a multiplexer configured to output to a single path comprising an odd number of inverters.
13 . A physically unclonable function (PUF) cell comprising:
a plurality of inverting stages arranged in an edge-chasing circuit; each inverting stage configured to enable a short circuit between outputs of a pair of inverters to enable accelerated aging of one of the inverters; and wherein a first of the inverting stages is configured to receive an aging value and a second of the inverting stages adjacent to the first of the inverting stages is configured to receive a complement of the aging value.
14 . The PUF cell of claim 13 , wherein the pair of inverters that a particular one of the inverting stages is configured to enable a short circuit between is comprised by the particular one of the inverting stages.
15 . The PUF cell of claim 13 , wherein a first inverter of the pair of inverters is comprised by a first one of the inverting stages and a second inverter of the pair of inverters is comprised by a second one of the inverting stages.
16 . The device of claim 13 , wherein at least some of the inverting stages comprise a diode-clamped inverter (DCI).
17 . The PUF cell of claim 16 , wherein a first inverter of the pair of inverters is a first DCI and a second inverter of the pair of inverters is a second DCI.
18 . The PUF cell of claim 16 , comprising a transmission gate configured to enable a short circuit between an output of a first DCI and an input of a second DCI.