Method and apparatus with circuit design parameter generation
A method of generating a circuit design parameter meeting a target specification, the method including generating a first probability distribution of a first specification using a first model provided a first parameter where the first model is configured to infer a correlation between the first parameter and the first probability distribution, generating a second parameter using a second model provided the first probability distribution, and updating the first model based on the second parameter. The second model is trained by using a reward, the reward being determined based on a second probability distribution of a second specification corresponding to the second parameter.
1 . A method of generating a circuit design parameter meeting a target specification, the method comprising:
generating a first probability distribution of a first specification using a first model provided a first parameter where the first model is configured to infer a correlation between the first parameter and the first probability distribution;
generating a second parameter using a second model provided the first probability distribution; and
updating the first model based on the second parameter,
wherein the second model is trained by using a reward, the reward being determined based on a second probability distribution of a second specification corresponding to the second parameter.
2 . The method of claim 1 , further comprising training the first model based on data obtained from a simulator outputting a third specification corresponding to a third parameter.
3 . The method of claim 1 , further comprising training the first model using training data that includes the first parameter with a third probability distribution, generated by a simulator provided with a third parameter being used as a ground truth.
4 . The method of claim 1 , wherein the first parameter is a virtual circuit design parameter.
5 . The method of claim 4 , wherein the second parameter obtained is another virtual circuit design parameter that is provided to the updated first model for further training of the first model.
6 . The method of claim 1 , further comprising training the second model, wherein the second specification is a state,
wherein respective operations of adjusting first parameters are actions, and
wherein the reward is based on the first probability distribution being determined based an increase in a previous action to a current action of adjusting the first parameter.
7 . The method of claim 6 , wherein the reward is determined based on a value obtained by subtracting a multiplication of a standard deviation of the first specification by a predetermined ratio from an average value of the first specification.
8 . The method of claim 6 , wherein the actions comprise an operation of adjusting each size of a plurality of transistors into respective different sizes.
9 . The method of claim 1 , further comprising training the second model, the training comprising assigning a high reward value in response to a standard deviation of the first specification being decreased compared to a previous standard deviation of a previous first probability distribution from the first model, and
wherein the first probability distribution comprises the standard deviation.
10 . The method of claim 1 , further comprising training the second model, the training comprising assigning a high reward value based on an average of specifications and a standard deviation of the first specification being increased compared to a previous average of specifications and standard deviation of the first specification.
11 . The method of claim 1 , further comprising training the first model, including training the first model to decrease a difference between a third specification obtained by applying the first parameter to a simulator and a first specification.
12 . The method of claim 1 , wherein the first parameter is the circuit design parameter.
13 . The method of claim 12 , wherein the circuit design parameter comprises a size of a transistor.
14 . The method of claim 12 , wherein the circuit design parameter comprises a size corresponding to each of a plurality of transistors.
15 . The method of claim 1 , further comprising:
transfer learning on the first model and the second model corresponding to a target specification and a new target specification including another specification.
16 . A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1 .
17 . An electronic device, comprising a processor configured to:
train a first model to infer a correlation between parameters and probability distributions with respect to a target circuit design specification;
generate a first probability distribution of a first specification by applying a first parameter as a circuit design parameter, to the first model;
generate a second parameter by applying the first probability distribution of the first specification to a second model; and
update the first model based on the second parameter,
wherein the second model is updated by using a reward determined based on a second probability distribution of a second specification corresponding to the second parameter.
18 . The electronic device of claim 17 , wherein the processor is further configured to perform updating of the second model, including using a first reward based on the first probability distribution.
19 . The electronic device of claim 18 , wherein the reward is further based on an action generated by an actor model provided at least the first probability distribution.
20 . The electronic device of claim 17 , wherein the training of the first model is dependent on ground truths generated by a circuit design simulator.