Pre-placement clocking identification and resolution for circuit designs

Inventors: Veeresh Pratap Singh (Hyderabad, IN); Padala V Santhosh (Hyderabad, IN); Srinivasan Dasasathyan (Secunderabad, IN)

Assignee: Xilinx, Inc.

G06F30/392

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Quick Facts

Patent No.: US 12711298
App. No.: 18/184,923
Granted: Aug 18, 2026
Kind: B2

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Abstract

Preplacement clock resolution for implementing a circuit design includes, prior to placement of the circuit design, determining, using computer hardware, pairs of clocks of the circuit design that clock synchronous inter-clock data paths. Using the computer hardware, a clock group is generated that includes clocks having a common ancestor clock node from the pairs of clocks. A clock delay group property is set, using the computer hardware, for the clocks of the clock group prior to placement. A placed version of the circuit design is generated using the computer hardware. The circuit design is placed using the clock delay group property as set for the clocks of the clock group.

Claims (33)

1 . A method, comprising:

prior to placement of a circuit design, determining, using computer hardware, a pair of clock signals specified by the circuit design that clocks a synchronous inter-clock data path, wherein the pair of clock signals have a common ancestor clock node;

generating, using the computer hardware, a clock group that includes the pair of clock signals;

setting, using the computer hardware, a clock delay group property for the clock signals of the clock group prior to placement, wherein the clock delay group property forces a placer to use a common location for a clock root for each clock signal of the clock group, and wherein the clock root of each clock signal is disposed between the common ancestor node and endpoints of the inter-clock data path; and

generating a placed version of the circuit design by placing, using the computer hardware, the circuit design using the clock delay group property as set for the clock signals of the clock group thereby locating the clock root for each clock signal of the pair of clock signals at the common location.

2 . The method of claim 1 , further comprising:

detecting a net of the circuit design as the synchronous inter-clock data path.

3 . The method of claim 1 , wherein each pair of clock signals includes a first clock signal used to clock a first endpoint of a net and a second clock signal used to clock a second endpoint of the net.

4 . The method of claim 1 , wherein the setting the clock delay group property forces the common location for the clock root of each clock signal of the clock group.

5 . The method of claim 4 , wherein during the placing, clock routing delays for the clock signals of the clock group are matched based on the respective clock roots of the clock signals of the clock group.

6 . The method of claim 5 , wherein the clock routing delays are determined from a clock buffer of each clock signal to the clock root for each clock signal.

7 . A system, comprising:

one or more hardware processors configured to initiate operations including:

prior to placement of a circuit design, determining a pair of clock signals specified by the circuit design that clocks a synchronous inter-clock data path, wherein the pair of clock signals have a common ancestor clock node;

generating a clock group that includes the pair of clock signals;

setting a clock delay group property for the clock signals of the clock group prior to placement, wherein the clock delay group property forces a placer to use a common location for a clock root for each clock signal of the clock group, and wherein the clock root of each clock signal is disposed between the common ancestor node and endpoints of the inter-clock data path; and

generating a placed version of the circuit design by placing the circuit design using the clock delay group property as set for the clock signals of the clock group thereby locating the clock root for each clock signal of the pair of clock signals at the common location.

8 . The system of claim 7 , wherein the one or more hardware processors are configured to initiate operations including:

detecting a net of the circuit design as the synchronous inter-clock data path.

9 . The system of claim 7 , wherein each pair of clock signals includes a first clock signal used to clock a first endpoint of a net and a second clock signal used to clock a second endpoint of the net.

10 . The system of claim 7 , wherein the setting the clock delay group property forces the common location for the clock root of each clock signal of the clock group.

11 . The system of claim 10 , wherein during the placing, clock routing delays for the clock signals of the clock group are matched based on the respective clock roots of the clock signals of the clock group.

12 . The system of claim 11 , wherein the clock routing delays are determined from a clock buffer of each clock signal to the clock root for each clock signal.

13 . A computer program product comprising one or more computer readable storage mediums having program instructions embodied therewith, wherein the program instructions are executable by computer hardware to cause the computer hardware to initiate executable operations comprising:

generating a clock group that includes the pair of clock signals;

14 . The computer program product of claim 13 , wherein the program instructions are executable by the computer hardware to cause the computer hardware to initiate executable operations comprising:

detecting a net of the circuit design as the synchronous inter-clock data path.

15 . The computer program product of claim 13 , wherein each pair of clock signals includes a first clock signal used to clock a first endpoint of a net and a second clock signal used to clock a second endpoint of the net.

16 . The computer program product of claim 13 , wherein during the placing, clock routing delays for the clock signals of the clock group are matched based on the respective clock roots of the clock signals of the clock group.

17 . The computer program product of claim 16 , wherein the clock routing delays are determined from a clock buffer of each clock signal to the clock root for each clock signal.