Method and system for use with an electronic design automation (EDA) tool to optimize clock scheduling
A method and computer-implemented system for use with an electronic design automation (EDA) tool to optimize clock scheduling. Based on an initial timing and area optimized design for a logic circuit, an optimal set of clock anchor points on a clock tree for the logic circuit, and slack statistics for a plurality of elements in the logic circuit, are determined. Clock skews for the CAPs associated with the plurality of elements are then scheduled as a function of the slack statistics. A refined timing and area optimized design for the logic circuit is generated based on the clock skews, and the refined timing and area optimized design is utilized as input to a clock tree synthesis module of the EDA tool.
1 . A method comprising:
determining a first design for a logic circuit;
determining a set of clock anchor points (CAPs) on a clock tree for the logic circuit based on the first design;
determining slack values on inputs and outputs of a plurality of groups of registers in the logic circuit;
scheduling clock skews for the CAPs associated with the plurality of groups of registers by determining slack values for the inputs and outputs of the plurality of groups of registers;
adding CAPs associated with groups of registers having positive slack values to a list of candidates;
generating a second design for the logic circuit based on the list of candidates; and
utilizing the second design as input to a clock tree synthesis module of an electronic design automation (EDA) tool.
2 . The method of claim 1 , wherein determining the first design comprises querying an EDA database containing output data from a place and router phase of the EDA tool.
3 . The method of claim 1 , further comprising advancing or delaying candidates on the list of candidates.
4 . The method of claim 3 , further comprising determining whether a clock signal for each CAP on the list of candidates should be advanced or delayed based on a maximum skew limit and a skew step.
5 . The method of claim 4 , further comprising deleting from the list of candidates CAPs associated with a group of registers having a slack value less than the skew step.
6 . The method of claim 3 , further comprising:
adding CAPs associated with registers having positive slack on both the input and the output to a first list of CAPs for which the clock signal can be advanced or delayed;
adding CAPs associated with registers having positive slack on only the input to a second list of CAPs for which the clock signal can be advanced; and
adding CAPs associated with registers having positive slack on only the output to a third list of CAPs for which the clock signal can be delayed.
7 . The method of claim 1 , further comprising converting the list of candidates to clock scheduling constraints for the EDA tool, the clock scheduling constraints serving as inputs to generating the second design for the logic circuit based on the clock skews.
8 . The method of claim 7 , further comprising building a clock tree for the logic circuit based on the clock scheduling constraints.
9 . A system comprising:
a processor; and
a memory storing instructions which, when executed by the processor, cause the processor to:
determine a first design for a logic circuit;
determine a set of clock anchor points (CAPs) on a clock tree for the logic circuit based on the first design;
determine slack values on inputs and outputs of a plurality of groups of registers in the logic circuit;
schedule clock skews for the CAPs associated with the plurality of groups of registers by determining slack values for the inputs and outputs of the plurality of groups of registers;
add CAPS associated with groups of registers having positive slack values to a list of candidates;
generate a second design for the logic circuit based on the list of candidates; and
utilize the second design as input to a clock tree synthesis module of an electronic design automation (EDA) tool.
10 . The system of claim 9 , wherein determining the first design comprises querying an EDA database containing output data from a place and router phase of the EDA tool.
11 . The system of claim 9 , the memory further storing instructions to cause the processor to advance or delay candidates on the list of candidates.
12 . The system of claim 11 , the memory further storing instructions to cause the processor to determine whether a clock signal for each CAP on the list of candidates should be advanced or delayed based on a maximum skew limit and a skew step.
13 . The system recited in claim 12 , further comprising instructions operative to delete from the list of candidates any CAPs associated with a group of registers having a slack value less than the skew step.
14 . The system of claim 13 , the memory further storing instructions to cause the processor to:
add CAPs associated with registers having positive slack on both the input and the output to a first list of CAPs for which the clock signal can be advanced or delayed;
add CAPs associated with registers having positive slack on only the input to a second list of CAPs for which the clock signal can be advanced; and,
add CAPs associated with registers having positive slack on only the output to a third list of CAPs for which the clock signal can be delayed.
15 . The system of claim 9 , the memory further storing instructions to cause the processor to convert the list of candidates to clock scheduling constraints for the EDA tool, the clock scheduling constraints serving as inputs to generate a refined timing and area optimized design for the logic circuit based on the clock skews.
16 . The system of claim 11 , the memory further storing instructions to cause the processor to build a clock tree for the logic circuit based on clock scheduling constraints.
17 . A non-transitory computer readable storage medium storing instructions that, when executed by at least one processor, cause the at least one processor to:
determine a first design for a logic circuit;
determine a set of clock anchor points (CAPs) on a clock tree for the logic circuit based on the first design;
determine slack values on inputs and outputs of a plurality of groups of registers in the logic circuit;
schedule clock skews for the CAPs associated with the plurality of groups of registers by determining slack values for the inputs and outputs of the plurality of groups of registers;
add CAPS associated with groups of registers having positive slack values to a list of candidates;
generate a second design for the logic circuit based on the list of candidates; and
utilize the second design as input to a clock tree synthesis module of an electronic design automation (EDA) tool.
18 . The non-transitory computer readable storage medium of claim 17 , the instructions to cause the at least one processor to advance or delay candidates on the list of candidates.
19 . The non-transitory computer readable storage medium of claim 18 , the instructions to cause the at least one processor to determine whether a clock signal for each CAP on the list of candidates should be advanced or delayed based on a maximum skew limit and a skew step.
20 . The non-transitory computer readable storage medium of claim 17 , instructions to cause the at least one processor to convert the list of candidates to clock scheduling constraints for the EDA tool, the clock scheduling constraints serving as inputs to generate a refined timing and area optimized design for the logic circuit based on the clock skews.