Display device, gate driving circuit and display driving method
A display device includes a display panel in which a plurality of gate lines are arranged in a first direction, and a plurality of subpixel arrays each including a plurality of subpixels are arranged in the first direction; a gate driving circuit including a first gate driving circuit located in one edge of the display panel and a second gate driving circuit located in another edge of the display panel, the first gate driving circuit and the second gate driving circuit sharing one gate line connected to one subpixel array; and a timing controller for controlling the gate driving circuit to operate in a defect detecting mode to detect a defect in the display panel during a blank periods in which at least one of the plurality of subpixels of the display panel does not emit light.
1 . A display device comprising:
a display panel in which a plurality of gate lines are arranged in a first direction, and a plurality of subpixel arrays each comprising a plurality of subpixels are arranged in the first direction;
a first gate driving circuit configured to supply a display scan signal through a gate line during an active period in a first bezel area of the display panel, where the at least one of the plurality of subpixels of the display panel emits light in the active period;
a second gate driving circuit configured to supply the display scan signal through the gate line during the active period in a second bezel area of the display panel; and
a timing controller configured to control the first gate driving circuit to supply a sensing scan signal through the gate line in a blank period of a defect detecting mode and control the second gate driving circuit to detect a defect in the display panel in which at least one of the plurality of subpixels of the display panel does not emit light using the sensing scan signal during the blank period of the defect detecting mode,
wherein the second gate driving circuit receives the sensing scan signal through an output node of the second gate driving circuit and transfers the received sensing scan signal to a defect detection circuit through a scan clock line in the defect detecting mode.
2 . The display device of claim 1 , wherein, in the defect detecting mode, the first gate driving circuit performs a sensing data writing operation for sensing one or more characteristic values of the at least one of the plurality of subpixels, and the second gate driving circuit performs a scan signal receiving operation of receiving the sensing scan signal supplied by the first gate driving circuit.
3 . The display device of claim 2 , wherein the second gate driving circuit comprises one or more selection switches for switching off a scan clock supplied to the scan clock line.
4 . The display device of claim 2 , wherein the defect detection circuit compares the sensing scan signal transferred by the second gate driving circuit with a reference voltage and detect whether the display panel has a defect.
5 . The display device of claim 4 , wherein the defect detection circuit comprises:
a detection switch configured to determine a detection time of the sensing scan signal transferred by the second gate driving circuit;
an amplifier comprising a non-inverting input terminal to which a reference voltage is applied, an inverting input terminal, and an output terminal;
an input resistor connected to the inverting input terminal; and
a feedback resistor connected between the inverting input terminal and the output terminal.
6 . The display device of claim 5 , wherein the detection switch is turned on after a settling time has elapsed from a time at which the sensing scan signal output at an output node of the first gate driving circuit transitions to a high level.
7 . The display device of claim 2 , wherein the first gate driving circuit further comprises: a level control circuit configured to control a voltage level of a scan clock line.
8 . The display device of claim 7 , wherein the level control circuit comprises:
a level control switch connected to the scan clock line;
a first resistor connected between the level control switch and a first terminal or line to which a high voltage is applied or supplied; and
a second resistor connected between the level control switch and a second terminal or line to which a low voltage is applied or supplied.
9 . The display device of claim 7 , wherein in the defect detecting mode, a voltage of the scan clock line equals to, or corresponds to, a level at which a corresponding subpixel is turned off.
10 . The display device of claim 7 , wherein in the defect detecting mode, a voltage of the scan clock line comprises a first level for turning on a corresponding subpixel among the plurality of subpixels and a second level to recovery a data voltage in a preceding frame or in a following frame.
11 . A gate driving circuit configured to drive a display panel in which a plurality of gate lines are arranged in a first direction, and a plurality of subpixel arrays each comprising a plurality of subpixels are arranged in the first direction, the gate driving circuit comprising:
a first gate driving circuit configured to supply a display scan signal through a gate line during an active period in a first bezel area of the display panel, where the at least one of the plurality of subpixels of the display panel emits light in the active period; and
a second gate driving circuit configured to supply the display scan signal through the gate line during the active period in a second bezel area of the display panel; and
wherein the first gate driving circuit supplies a sensing scan signal through the gate line in a blank period of a defect detecting mode and the second gate driving circuit detects a defect in the display panel in which at least one of the plurality of subpixels of the display panel does not emit light using the sensing scan signal during the blank period of the defect detecting mode,
wherein the second gate driving circuit receives the sensing scan signal through an output node of the second gate driving circuit and transfers the received sensing scan signal to a defect detection circuit through a scan clock line in the defect detecting mode.
12 . The gate driving circuit of claim 11 , wherein, in the defect detecting mode, the first gate driving circuit performs a sensing data writing operation for sensing one or more characteristic values of the at least one of the plurality of subpixels, and the second gate driving circuit performs a scan signal receiving operation of receiving the sensing scan signal supplied by the first gate driving circuit.
13 . The gate driving circuit of claim 12 , wherein the second gate driving circuit comprises one or more selection switches for switching off a scan clock supplied to the scan clock line.
14 . The gate driving circuit of claim 12 , wherein the first gate driving circuit further comprises: a level control circuit for controlling a voltage level of a scan clock line.
15 . The gate driving circuit of claim 14 , wherein the level control circuit comprises:
a level control switch connected to the scan clock line;
a first resistor connected between the level control switch and a first terminal or line to which a high voltage is applied or supplied; and
a second resistor connected between the level control switch and a second terminal or line to which a low voltage is applied or supplied.
16 . The gate driving circuit of claim 11 , wherein the gate driving circuit comprising:
a line selector configured to charge an M node based on a carry signal of a preceding stage in response to an application of a line sensing signal;
a Q node controller configured to charge a Q node to a level of a first high level gate voltage in response to the carry signal of the preceding stage, and to discharge the Q node to a level of a third low level gate voltage in response to an application of a carry signal of a following stage;
a Q node stabilizer configured to discharge the Q node and a QH node to the level of the third low level gate voltage in response to a voltage of a QB node;
an inverter configured to change a level of the voltage of the QB node based on a level of the voltage of the Q node;
a QB node stabilizer configured to discharge the QB node to the level of the third low level gate voltage in response to the carry signal of the following stage, a reset signal, and a charging voltage of the M node;
a carry signal generator configured to output a carry signal based on a voltage level of a carry clock or the level of the third low level gate voltage based on the level of the voltage of the Q node or the level of the voltage of the QB node; and
a scan signal generator configured to output a plurality of scan signals based on a voltage level of a plurality of scan clocks or the level of a first low level gate voltage based on the level of the voltage of the Q node or the level of the voltage of the QB node.
17 . The gate driving circuit of claim 16 , wherein in the defect detecting mode, the Q node in the second gate driving circuit is remained at a high level.
18 . A method of driving a display panel in which a plurality of gate lines are arranged in a first direction, and a plurality of subpixel arrays each comprising a plurality of subpixels are arranged in the first direction, the method comprising:
during an active period in which at least one of the plurality of the subpixels of the display panel emits light, controlling a first gate driving circuit located in a first edge of the display panel to supply a display scan signal through a gate line and a second gate driving circuit located in a second edge of the display panel to supply the display scan signal through the gate line; and
during a blank period in which the at least one of the plurality of the subpixels of the display panel does not emit light, controlling the first gate driving circuit to supply a sensing scan signal through the gate line in a defect detecting mode and controlling the second gate driving circuit to receive the sensing scan signal through a output node of the second gate driving circuit and to transfer the received sensing scan signal to a defect detection circuit through a scan clock line in the defect detecting mode.