Data voltage supply circuit, display device and driving method

1 . A data voltage supply circuit, applied to a display device, wherein:

the display device comprises a data driver, a plurality of columns of pixels and a plurality of columns data lines, a column of pixels comprises M columns of sub-pixels; M is an integer greater than or equal to 3; the data driver comprises a plurality of data voltage supply terminals; the data voltage supply circuit comprises a plurality of supply circuits;

a supply circuit is configured to control the M columns of sub-pixels comprised in a corresponding column of pixels to respectively receive a data voltage provided by a corresponding data voltage supply terminal, or to control the M columns of sub-pixels comprised in the corresponding column of pixels to obtain the data voltage provided to the M columns of sub-pixels according to a data voltage provided to at least one other column of pixels;

the supply circuit comprises a first gating circuit and a second gating circuit; the column of sub-pixels are electrically connected to a corresponding column data line, and receive the data voltage through the corresponding column data line;

the first gating circuit is electrically connected to the M data voltage supply terminals and current M columns data lines respectively, and is configured to control to connect or disconnect an mth data voltage supply terminal among the M data voltage supply terminals and an mth data line among the current M columns data lines; the mth data line is electrically connected to the mth column of sub-pixels in the M columns of sub-pixels comprised in the corresponding column of pixels; m is a positive integer less than or equal to M;

the second gating circuit is respectively electrically connected to the current M columns data lines, a first group of M columns data lines electrically connected to the M columns of sub-pixels comprised in a first target column of pixels, and a second group of M columns data lines electrically connected to M columns of the sub-pixels comprised in a second target column of pixels, configured to control the data voltages received by the current M columns data lines according to the data voltage received by the first group of M columns data line and the data voltage received by the second group of M columns data lines;

the first target column of pixels is a column of pixels except the corresponding column of pixels, the second target column of pixels is a column of pixels except the corresponding column of pixels, the first target column of pixels and the second target column of pixels are different columns of pixels;

the current M columns data lines are data lines electrically connected to the M columns of sub-pixels comprised in the corresponding column of pixels; and

the data lines electrically connected to the M columns of sub-pixels in the first target column of pixels are directly electrically connected to a corresponding data voltage supply terminal, and the data lines electrically connected to the M columns of sub-pixels in the second target column of pixels are directly electrically connected to a corresponding data voltage supply terminal.

2 . The data voltage supply circuit according to claim 1 , wherein the first gating circuit comprises M first switch circuits;

an mth first switch circuit is electrically connected to the mth data voltage supply terminal among the M data voltage supply terminals and the mth data line among the current M columns data lines, respectively, and is configured to control to connect or disconnect the mth data voltage supply terminal and the mth data line.

3 . The data voltage supply circuit according to claim 2 , wherein the mth first switching circuit comprises the mth first switching transistor;

a gate electrode of the mth first switching transistor is electrically connected to a first control voltage terminal, a first electrode of the mth first switching transistor is electrically connected to the mth data voltage supply terminal, and a second electrode of the mth first switching transistor is electrically connected to the mth data line;

the data voltage supply circuit comprises a first control circuit;

the first control circuit is configured to provide a first control voltage to the first control voltage terminal to control the mth first switching transistor to be turned on or off.

4 . The data voltage supply circuit according to claim 1 , wherein the second gating circuit comprises M second switch circuits, M first resistors, M third switch circuits and M second resistors;

an mth second switch circuit is electrically connected to the mth column data line in the first group of M columns data lines and a first terminal of the mth first resistor, respectively, and is configured to control to connect or disconnect the mth column data line in the first group of M columns data lines and the first terminal of the mth first resistor; a second terminal of the mth first resistor is electrically connected to the mth column data line in the current M columns data lines;

a first terminal of the mth second resistor is electrically connected to the mth column data line among the current M columns data lines, and the mth third switch circuit is respectively electrically connected to the second terminal of the mth second resistor and the mth column data line in the second group of M columns data lines, and is configured to control to connect or disconnect the second terminal of the mth second resistor and the mth column data line in the second group of M columns data lines.

5 . The data voltage supply circuit according to claim 4 , wherein the mth second switching circuit comprises an mth second switching transistor, and the mth third switching circuit comprises an mth third switching transistor;

a gate electrode of the mth second switching transistor is electrically connected to a second control voltage terminal, and a first electrode of the mth second switching transistor is connected to the mth column data in the first group of M columns data lines, a second electrode of the mth second switching transistor is electrically connected to the first terminal of the mth first resistor;

a gate electrode of the mth third switching transistor is electrically connected to the second control voltage terminal, and a first electrode of the mth third switching transistor is electrically connected to the second terminal of the mth second resistor, a second electrode of the mth third switching transistor is electrically connected to the mth column data line in the second group of M columns data lines;

the data voltage supply circuit comprises a second control circuit;

the second control circuit is configured to provide a second control voltage to the second control voltage terminal to control the mth second switching transistor to be turned on or off, and to control the mth third switching transistor to be turned on or off.

6 . The data voltage supply circuit according to claim 1 , wherein the data driver comprises at least one data driving circuit; the column of pixels comprises three columns of sub-pixels;

the data driving circuit comprises N data voltage supply terminals; N is a positive integer;

an ath supply circuit comprises an ath first gating circuit and an ath second gating circuit; a is a positive integer;

a first column of sub-pixels comprised in a (3a−1)th column of pixels is electrically connected to a (6a−2)th column data line, a second column of sub-pixels comprised in the (3a−1)th column of pixels is electrically connected to a (6a−1)th column data line, and a third column of sub-pixels include comprised in the (3a−1)th column data line is electrically connected to a 6ath column data line;

a first column of sub-pixels include comprised in a (3a−2)th column of pixels is electrically connected to a (6a−5)th column data line, a second column of sub-pixels include comprised in the (3a−2)th column of pixels is electrically connected to a (6a−4)th column data line, and a third column of sub-pixels include comprised in the (3a−2)th column data line is electrically connected to a (6a−3)th column data line;

a first column of sub-pixels include comprised in a 3ath column of pixels is electrically connected to a (6a+1)th column data line, a second column of sub-pixels include comprised in the 3ath column of pixels is electrically connected to a (6a+2)th column data line, and a third column of sub-pixels include comprised in the 3ath column data line is electrically connected to a (6a+3)th column data line;

the ath first gating circuit is respectively connected to the (6a−2)th column data line, the (6a−1)th column data line, the 6ath column data line, a (6a−2)th data voltage supply terminal, a (6a−1)th data voltage supply terminal, and a 6ath data voltage supply terminal, and is configured to control to connect or disconnect the (6a−2)th column data line and the (6a−2)th data voltage supply terminal, control to connect or disconnect the (6a−1)th column data line and the (6a−1)th data voltage supply terminal, and control to connect or disconnect the bath column data line and the 6ath data voltage supply terminal;

the ath second gating circuit is respectively electrically connected to the (6a−5)th column data line, the (6a−4)th column data line, the (6a−3)th column data line, the (6a+1)th column data line, the (6a+2)th column data line and the (6a+3)th column data line, the (6a−2)th column data line, the (6a−1)th column of data line and the 6ath column data line, and is configured to control the data voltage received by the (6a−2)th column data line according to the data voltage received by the (6a−5)th column data line and the data voltage received by the (6a+1)th column data line, control the data voltage received by the the (6a−1)th column data line according to the data voltage received by the (6a−4)th column data line and the data voltage received by the (6a+2)th column data line, control the data voltage received by the 6ath column data line according to the data voltage received by the (6a−3)th column data line and the data voltage received by the (6a+3)th column data line;

the (6a−5)th column data line is directly electrically connected to the (6a−5)th data voltage supply terminal, the (6a−4)th column data line is directly electrically connected to the (6a−4)th data voltage supply terminal, the (6a−3)th column data line is directly electrically connected to the (6a−3)th data voltage supply terminal, the (6a+1)th column data line is directly electrically connected to the (6a+1)th data voltage supply terminal, the (6a+2)th column data line is directly electrically connected to the (6a+2)th data voltage supply terminal, the (6a+3)th column data line is directly electrically connected to the (6a+3)th data voltage supply terminal.

7 . The data voltage supply circuit according to claim 6 , wherein N is multiple of 6;

the data voltage supply circuit comprises a fourth gating circuit;

the fourth gating circuit is respectively connected to an Nth column data line, an (N−1)th column data line, an (N−2)th column data line, an (N−3)th column data line, an (N−4)th column data line and an (N−5)th column data line, configured to control to connect or disconnect the Nth column data line and the (N−3)th column data line, and control to connect or disconnect the (N-1) th column data line and the (N−4)th column data line, and control to connect or disconnect the (N−2)th column data line and the (N−5)th column data line.

8 . The data voltage supply circuit according to claim 6 , wherein N is multiple of 6, and the data driver comprises B data driver circuits; B is an integer greater than 1;

a bth data driving circuit is electrically connected to a bth group of N columns data lines, a (b+1)th data circuit is electrically connected to a (b+1)th group of N columns data lines, b is a positive integer, and b+1 is less than or equal to B;

the data voltage supply circuit comprises a fifth gating circuit;

the fifth gating circuit is respectively connected to the (N−5)th data line in the bth group of N columns data lines, the (N−4)th data line in the bth group of N columns data lines, and the (N−3) th data line in the bth group of N columns data lines, the (N−2)th data line in the bth group of N columns data lines, the (N−1)th data line in the bth group of N columns data lines, the Nth data line in the bth group of N columns data lines, a first column data line in the (b+1)th group of N columns data lines, a second column data line in the (b+1)th group of N columns data lines, and a third column data line in the (b+1)th group of N columns data lines, and is configured to control the data voltage received by the (N−2)th data line in the bth group of N columns data lines according to the data voltage received by the (N−5)th data line in the bth group of N columns data lines and the first column data line in the (b+1)th group of N columns data lines, control the data voltage received by the (N−1)th data line in the bth group of N columns data lines according to the data voltage received by the (N−4)th data line in the bth group of N columns data lines and the data voltage received by the second column data line in the (b+1)th group of N columns data lines, control the data voltage received by the Nth data line in the bth group of N columns data lines according to the data voltage received by the (N−3)th data line in the bth group of N columns data lines and the data voltage received by the third column data line in the (b+1)th group of N columns data lines.

9 . A display device, comprising a plurality of rows gate lines, a plurality of columns data lines, a plurality of rows and a plurality of columns of pixels, a driving circuit and the data voltage supply circuit according to claim 1 ; wherein the driving circuit is electrically connected to the plurality of rows gate lines, and configured to provide a driving signals to the gate line;

pixels located in a same row are electrically connected to a corresponding row gate line, configured to receive the driving signal provided by the corresponding row gate line;

pixels located in a same column are electrically connected to a corresponding column data line, configured to receive the data voltage from the corresponding column data line.

10 . A driving method, applied to the display device according to claim 9 , wherein the driving method comprises:

during a driving period, providing, by the driving circuit, the driving signal to the gate line to control a plurality of rows scanning lines to be turned on sequentially;

during the driving period, there being an overlapping time period and a non-overlapping time period between valid time periods of scanning signals provided by at least two adjacent gate lines among the plurality of rows gate lines that are turned on sequentially;

the data voltage received by the data line during at least part of the overlapping time period being the same as the data voltage received by the data line during at least part of the non-overlapping time period.

11 . A driving method, applied to the display device according to claim 9 , wherein the driving cycle comprises a plurality of driving phases arranged sequentially; a (2n−1)th row scanning signal provided by a (2n−1)th row scanning line is the same as a 2nth row scanning signal provided by a 2nth row scanning line; the driving method comprises:

in an nth driving phase, the (2n−1)th row scan line and the 2nth row scan line being turned on, and the (2n−1)th row of sub-pixels and the 2nth row of sub-pixels receiving the data voltage provided by the corresponding data line;

n is a positive integer.

12 . The display device according to claim 9 , wherein the first gating circuit comprises M first switch circuits;

an mth first switch circuit is electrically connected to the mth data voltage supply terminal among the M data voltage supply terminals and the mth data line among the current M columns data lines, respectively, and is configured to control to connect or disconnect the mth data voltage supply terminal and the mth data line.

13 . The display device according to claim 9 , wherein the second gating circuit comprises M second switch circuits, M first resistors, M third switch circuits and M second resistors;

an mth second switch circuit is electrically connected to the mth column data line in the first group of M columns data lines and a first terminal of the mth first resistor, respectively, and is configured to control to connect or disconnect the mth column data line in the first group of M columns data lines and the first terminal of the mth first resistor; a second terminal of the mth first resistor is electrically connected to the mth column data line in the current M columns data lines;

a first terminal of the mth second resistor is electrically connected to the mth column data line among the current M columns data lines, and the mth third switch circuit is respectively electrically connected to the second terminal of the mth second resistor and the mth column data line in the second group of M columns data lines, and is configured to control to connect or disconnect the second terminal of the mth second resistor and the mth column data line in the second group of M columns data lines.

14 . A data voltage supply circuit, applied to a display device, wherein:

the display device comprises a data driver, a plurality of columns of pixels and a plurality of columns data lines, a column of pixels comprises M columns of sub-pixels; M is an integer greater than or equal to 3; the data driver comprises a plurality of data voltage supply terminals; the data voltage supply circuit comprises a plurality of supply circuits;

a supply circuit is configured to control the M columns of sub-pixels comprised in a corresponding column of pixels to respectively receive a data voltage provided by a corresponding data voltage supply terminal, or to control the M columns of sub-pixels comprised in the corresponding column of pixels to obtain the data voltage provided to the M columns of sub-pixels according to a data voltage provided to at least one other column of pixels;

the data driver comprises at least one data driving circuit; the column of pixels comprises three columns of sub-pixels;

the data driving circuit comprises N data voltage supply terminals; N is a positive integer;

an ath supply circuit comprises an ath first gating circuit and an ath second gating circuit; a is a positive integer;

a first column of sub-pixels comprised in a (3a−1)th column of pixels is electrically connected to a (6a−2)th column data line, a second column of sub-pixels comprised in the (3a−1)th column of pixels is electrically connected to a (6a−1)th column data line, and a third column of sub-pixels comprised in the (3a−1)th column data line is electrically connected to a bath column data line;

a first column of sub-pixels comprised in a (3a−2)th column of pixels is electrically connected to a (6a−5)th column data line, a second column of sub-pixels comprised in the (3a−2)th column of pixels is electrically connected to a (6a−4)th column data line, and a third column of sub-pixels comprised in the (3a−2)th column data line is electrically connected to a (6a−3)th column data line;

a first column of sub-pixels comprised in a 3ath column of pixels is electrically connected to a (6a+1)th column data line, a second column of sub-pixels comprised in the 3ath column of pixels is electrically connected to a (6a+2)th column data line, and a third column of sub-pixels comprised in the 3ath column data line is electrically connected to a (6a+3)th column data line;

the ath first gating circuit is respectively connected to the (6a−2)th column data line, the (6a−1)th column data line, the bath column data line, a (6a−2)th data voltage supply terminal, a (6a−1)th data voltage supply terminal, and a 6ath data voltage supply terminal, and is configured to control to connect or disconnect the (6a−2)th column data line and the (6a−2)th data voltage supply terminal, control to connect or disconnect the (6a−1)th column data line and the (6a−1)th data voltage supply terminal, and control to connect or disconnect the 6ath column data line and the 6ath data voltage supply terminal;

the ath second gating circuit is respectively electrically connected to the (6a−5)th column data line, the (6a−4)th column data line, the (6a−3)th column data line, the (6a+1)th column data line, the (6a+2)th column data line and the (6a+3)th column data line, the (6a−2)th column data line, the (6a−1)th column of data line and the 6ath column data line, and is configured to control the data voltage received by the (6a−2)th column data line according to the data voltage received by the (6a−5)th column data line and the data voltage received by the (6a+1)th column data line, control the data voltage received by the the (6a−1)th column data line according to the data voltage received by the (6a−4)th column data line and the data voltage received by the (6a+2)th column data line, control the data voltage received by the bath column data line according to the data voltage received by the (6a−3)th column data line and the data voltage received by the (6a+3)th column data line; and

the (6a−5)th column data line is directly electrically connected to the (6a−5)th data voltage supply terminal, the (6a−4)th column data line is directly electrically connected to the (6a−4)th data voltage supply terminal, the (6a−3)th column data line is directly electrically connected to the (6a−3)th data voltage supply terminal, the (6a+1)th column data line is directly electrically connected to the (6a+1)th data voltage supply terminal, the (6a+2)th column data line is directly electrically connected to the (6a+2)th data voltage supply terminal, the (6a+3)th column data line is directly electrically connected to the (6a+3)th data voltage supply terminal.