Level shift assembly, method for over-current protection, and display apparatus

1 . A level shift assembly for use in a display apparatus, comprising a level shift module, wherein the level shift module comprises a control unit, a current detection unit, a level shift unit, and an over-current protection unit;

the level shift unit is configured to acquire a digital clock signal and acquire a plurality of analog clock signals based on the digital clock signal;

the control unit is configured to determine, at a first falling edge of the digital clock signal, a first analog clock signal among the analog clock signals which corresponds to the first falling edge based on a correspondence of a current display mode, wherein the correspondence is between falling edges of the digital clock signal and the analog clock signals, and a moment, at which the falling edge of the digital clock signal is present, is within a last line period of a plurality of sequential line periods of one of a high-level period and a low-level period of a corresponding analog clock signal;

the control unit is configured to control the current detection unit to detect a current of the first analog clock signal; and

the current detection unit is configured to send an over-current detection signal to the over-current protection unit when the current of the first analog clock signal is not within a current threshold range.

2 . The level shift assembly according to claim 1 , wherein the level shift module further comprises a falling edge trigger, which is configured to monitor the digital clock signal and send a falling edge detection signal to the control unit when a falling edge of the digital clock signal is detected.

3 . The level shift assembly according to claim 2 , wherein the control unit comprises a shift register, which is electrically connected to the falling edge trigger and is configured to control, under trigger of the falling edge detection signal and based on the correspondence between falling edges of the digital clock signal and the analog clock signals, the current detection unit to detect a current of the analog clock signal corresponding to the falling edge.

4 . The level shift assembly according to claim 3 , wherein the control unit further comprises a controller and a shift matrix circuit electrically which is connected to the shift matrix circuit;

the shift matrix circuit is electrically connected to the shift register and the current detection unit, respectively;

the current detection unit comprises a plurality of current detection subunits, which are configured to detect currents of the plurality of analog clock signals, respectively; and

the controller is configured to control the shift matrix circuit to switch on a connection between the shift register and a first current detection subunit among the current detection subunits at the first falling edge, and the first current detection subunit is configured to detect the current of the first analog clock signal under control of the shift register.

5 . The level shift assembly of claim 4 , wherein each of the current detection subunits comprises a switch sub-subunit and a current detection sub-subunit, and the switch sub-subunit is electrically connected to the current detection sub-subunit and is electrically connected to the shift matrix circuit; and

the shift register is configured to send an switch-on signal to the shift matrix circuit when receiving the falling edge detection signal, in order that the shift matrix circuit transmits the switch-on signal to a switch unit in the first current detection subunit, and the switch sub-subunit is configured to turn on a current detection sub-subunit in the first current detection subunit.

6 . The level shift assembly according to claim 4 , wherein the level shift module further comprises a memory, clock signal data being stored in the memory; the clock signal data comprise data of the plurality of analog clock signals and data of the digital clock signal; the memory is electrically connected to the controller; the controller is configured to control the shift matrix circuit based on the clock signal data, such that the shift matrix circuit switch on the connection between the shift register and the first current detection subunit among the current detection subunits at the first falling edge.

7 . The level shift assembly according to claim 6 , wherein the clock signal data comprise a number of cycles of the analog clock signals, and the controller is configured to control the shift register based on the number of cycles of the analog clock signals, such that a number of bits of the shift register is the same as the number of cycles of the analog clock signals.

8 . The level shift assembly according to claim 6 , wherein the shift matrix circuit comprises a plurality of input channels and a plurality of output channels, the plurality of input channels being electrically connected to the shift register, and the plurality of output channels being electrically connected to the plurality of current detection subunits;

the controller is further configured to determine, among a plurality of preset display modes, a target display mode matching the current display mode, the plurality of preset display modes each having a corresponding correspondence, which comprises connecting relationships between the plurality of input channels and the plurality of output channels; and

the controller is further configured to control the shift matrix circuit based on a corresponding correspondence of the target display mode.

9 . The level shift assembly according to claim 3 , wherein the display apparatus comprises a frame start signal line, and the level shift module further comprises a reset unit, which is electrically connected to the frame start signal line and the shift register, respectively; and

the reset unit is configured to reset the shift register when receiving a frame start signal from the frame start signal line.

10 . The level shift assembly according to claim 9 , wherein the reset unit comprises a rising edge trigger and a reset switch; the rising edge trigger is electrically connected to the frame start signal line and the reset switch, respectively, and the reset switch is electrically connected to the shift register.

11 . The level shift assembly according to claim 1 , wherein the display apparatus comprises at least two digital clock signal lines; the control unit has a number of at least two; and the at least two control units are electrically connected to the at least two digital clock signal lines in one-to-one correspondence.

12 . The level shift assembly according to claim 1 , wherein the display apparatus comprises one digital clock signal line; the control unit has a number of one; and the control unit is electrically connected to the one digital clock signal line.

13 . The level shift assembly according to claim 1 , wherein the digital clock signal comprises a first digital clock signal and a second digital clock signal; the level shift unit is configured to acquire, based on the first digital clock signal and the second digital clock signal, the plurality of analog clock signals arranged sequentially; and for any two adjacent analog clock signals among the analog clock signals, a latter analog clock signal lags one line period behind a previous analog clock signal.

14 . The level shift assembly according to claim 1 , wherein the level shift module has a number of 2, the two level shift modules comprising a first level shift module and a second level shift module, the first level shift module and the second level shift module are configured to jointly generate n analog clock signals, and for any two adjacent analog clock signals of the n analog clock signals, a latter analog clock signal lags one line period behind a previous analog clock signal;

a level shift unit in the first level shift module is configured to acquire a first digital clock signal and a second digital clock signal, and generates odd-numbered analog clock signals among the n analog clock signals based on the first digital clock signal and the second digital clock signal;

a level shift unit in the second level shift unit is configured to acquire a third digital clock signal and a fourth digital clock signal, and generates even-numbered analog clock signals among the n analog clock signals based on the third digital clock signal and the fourth digital clock signal; and

the first digital clock signal, the second digital clock signal, the third digital clock signal and the fourth digital clock signal each have a duty cycle greater than 50%.

15 . The level shift assembly according to claim 1 , wherein the level shift module has a number of 2, the two level shift modules comprising a first level shift module and a second level shift module, the first level shift module and the second level shift module are configured to jointly generate n analog clock signals, the n analog clock signals comprise a plurality of analog clock signal sets, each of which comprises two adjacent analog clock signals, and for any two adjacent analog clock signal sets, a latter analog clock signal set lags one line period behind a previous analog clock signal set;

a level shift unit in the first level shift module is configured to acquire a first digital clock signal and a second digital clock signal, and generate odd-numbered analog clock signals among the n analog clock signals based on the first digital clock signal and the second digital clock signal; and

a level shift unit in the second level shift module is configured to acquire a third digital clock signal and a fourth digital clock signal, and generate even-numbered analog clock signals among the n analog clock signals based on the third digital clock signal and the fourth digital clock signal.

16 . The level shift assembly according to claim 1 , wherein the digital clock signal comprises a first digital clock signal; the level shift unit is configured to acquire, based on the first digital clock signal, the plurality of analog clock signals arranged sequentially; and for any two adjacent analog clock signals among the analog clock signals, a latter analog clock signal lags one line period behind a previous analog clock signal.

17 . The level shift assembly according to claim 1 , wherein the display apparatus comprises a drive circuit, which is configured to acquire the plurality of analog clock signals output by the level shift unit and to drive, based on the plurality of analog clock signals, the display apparatus to display; and

the over-current protection unit is configured to determine, when the over-current detection signal is received, whether over-current occurs based on the over-current detection signal.

18 . A method for over-current protection for use in the lift shift assembly according to claim 1 , comprising:

acquiring a digital clock signal, and acquiring a plurality of analog clock signals based on the digital clock signal;

determining, at a first falling edge of the digital clock signal, a first analog clock signal among the analog clock signals which corresponds to the first falling edge based on a correspondence, wherein the correspondence is between falling edges of the digital clock signal and the analog clock signals, and a moment, at which the falling edge of the digital clock signal is present, is within a last line period of a plurality of sequential line periods of one of a high-level period and a low-level period of a corresponding analog clock signal;

detecting a current of the first analog clock signal; and

performing over-current protective detection when the current of the first analog clock signal is not within a current threshold range.

19 . The display apparatus, comprising a display panel and the level shift assembly according to claim 1 .

20 . The display apparatus according to claim 19 , further comprising a timing controller and a drive circuit, wherein the level shift assembly is electrically connected to the timing controller and the drive circuit, respectively; the timing controller is configured to provide a digital clock signal to the level shift assembly; and the drive circuit is configured to drive the display panel based on analog clock signals provided by the level shift assembly.