Pixel driving circuit and driving method therefor, display panel, and display device

1 . A display panel, comprising a pixel driving circuit for driving a light-emitting unit, the pixel driving circuit comprising:

a driving transistor;

a second transistor, having a first electrode connected to a gate of the driving transistor, a second electrode connected to a second electrode of the driving transistor, and a gate connected to a gate line;

a fourth transistor, having a first electrode connected to a data line, a second electrode connected to a first electrode of the driving transistor, and a gate connected to a second enable signal line;

a fifth transistor, having a first electrode connected to a power supply line, a second electrode connected to the first electrode of the driving transistor, and a gate connected to a first enable signal line;

a sixth transistor, having a first electrode connected to the second electrode of the driving transistor, a second electrode connected to a first electrode of the light-emitting unit, and a gate connected to the first enable signal line;

wherein the display panel further comprises:

a base substrate;

an active layer, located on a side of the base substrate, wherein the active layer comprises a second active part, a third active part, a fourth active part, a fifth active part and a sixth active part, the second active part is configured to form a channel region of the second transistor, the third active part is configured to form a channel region of the driving transistor, the fourth active part is configured to form a channel region of the fourth transistor, the fifth active part is configured to form a channel region of the fifth transistor, and the sixth active part is configured to form a channel region of the sixth transistor;

a first conductive layer, located on a side of the active layer away from the base substrate, wherein the first conductive layer comprises the first enable signal line, the second enable signal line, the gate line and a first conductive part,

wherein an orthographic projection of the first conductive part on the base substrate covers an orthographic projection of the third active part on the base substrate, and the first conductive part is configured to form the gate of the driving transistor;

wherein an orthographic projection of the first enable signal line on the base substrate extends along a first direction and covers an orthographic projection of the fifth active part on the base substrate and an orthographic projection of the sixth active part on the base substrate, and a partial structure of the first enable signal line is configured to form the gate of the fifth transistor and the gate of the sixth transistor;

wherein an orthographic projection of the second enable signal line on the base substrate extends along the first direction and covers an orthographic projection of the fourth active part on the base substrate, and a partial structure of the second enable signal line is configured to form the gate of the fourth transistor;

wherein an orthographic projection of the gate line on the base substrate extends along the first direction and covers an orthographic projection of the second active part on the base substrate, and a partial structure of the gate line is configured to form the gate of the second transistor.

2 . The display panel according to claim 1 , wherein the pixel driving circuit further comprises:

a capacitor, connected between that power supply line and the gate of the driving transistor;

a first transistor, having a first electrode connected to a first initial signal line, a second electrode connected to the gate of the driving transistor, and a gate connected to a reset signal line;

a seventh transistor, having a first electrode connected to a second initial signal line, a second electrode connected to the first electrode of the light-emitting unit, and a gate connected to the second enable signal line;

wherein the driving transistor, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are P-type transistors;

wherein the active layer further comprises a first active part and a seventh active part, the first active part is configured to form a channel region of the first transistor, and the seventh active part is configured to form a channel region of the seventh transistor;

wherein the first conductive layer further comprises a reset signal line, an orthographic projection of the reset signal line on the base substrate extends along the first direction, the orthographic projection of the reset signal line on the base substrate covers an orthographic projection of the first active part on the base substrate, and a partial structure of the reset signal line is configured to form the gate of the first transistor;

wherein the orthographic projection of the second enable signal line on the base substrate further covers the seventh active part, and a partial structure of the second enable signal line is configured to form the gate of the seventh transistor;

wherein the display panel further comprises a second conductive layer, the second conductive layer is located on a side of the first conductive layer away from the base substrate, and the second conductive layer comprises:

a second conductive part, wherein an orthographic projection of the second conductive part on the base substrate at least partially overlaps with the orthographic projection of the first conductive part on the base substrate, the first conductive part is further configured to form a first electrode of the capacitor, and the second conductive part is further configured to form a second electrode of the capacitor;

wherein the orthographic projection of the gate line on the base substrate is located on a side of the orthographic projection of the first conductive part on the base substrate away from the orthographic projection of the first enable signal line on the base substrate;

wherein the orthographic projection of the reset signal line on the base substrate is located on a side of the orthographic projection of the gate line on the base substrate away from the orthographic projection of the first conductive part on the base substrate.

3 . The display panel according to claim 2 , wherein the active layer further comprises a tenth active part and an eleventh active part, the tenth active part is connected to an end of the first active part away from the second active part, and the eleventh active part is connected to an end of the seventh active part away from the sixth active part;

the second conductive layer further comprises:

the first initial signal line, wherein an orthographic projection of the first initial signal line on the base substrate extends along the first direction, and the orthographic projection of the first initial signal line on the base substrate is located on a side of the orthographic projection of the reset signal line on the base substrate away from the orthographic projection of the first conductive part on the base substrate;

the second initial signal line, wherein an orthographic projection of the second initial signal line on the base substrate extends along the first direction, and the orthographic projection of the second initial signal line on the base substrate is located on a side of the orthographic projection of the second enable signal line on the base substrate away from the orthographic projection of the first conductive part on the base substrate;

wherein the display panel further comprises a third conductive layer, the third conductive layer is located on a side of the second conductive layer away from the base substrate, and the third conductive layer comprises:

a second connection part, connecting the tenth active part and the first initial signal line through a via hole respectively;

a third connection part, connecting the second initial signal line and the eleventh active part through a via hole respectively,

wherein the first direction is a row direction, and the display panel comprises a plurality of rows of pixel driving circuits, and an orthographic projection of the second initial signal line in the pixel driving circuit of a current row on the base substrate is located between an orthographic projection of the reset signal line in the pixel driving circuit of an adjacent next row on the base substrate and an orthographic projection of the gate line on the base substrate.

4 . The display panel according to claim 2 , wherein the first active part comprises a first active sub-part and a second active sub-part, and the active layer further comprises a third active sub-part connected between the first active sub-part and the second active sub-part;

an orthographic projection of the first initial signal line on the base substrate at least partially overlaps with an orthographic projection of the third active sub-part on the base substrate.

5 . The display panel according to claim 2 , wherein the second active part comprises a fourth active sub-part and a fifth active sub-part, and the active layer further comprises a sixth active sub-part connected between the fourth active sub-part and the fifth active sub-part;

wherein the second initial signal line comprises:

a main body line, wherein an orthogonal projection of the main body line on the base substrate extends along the first direction;

a first protrusion part, connected to the main body line, wherein an orthographic projection of the first protrusion part on the base substrate extends along a second direction, and the second direction intersects with the first direction;

wherein, an orthographic projection of the first protrusion part in the pixel driving circuit of a previous row on the base substrate at least partially overlaps with an orthographic projection of the sixth active sub-part in the pixel driving circuit of a current row on the base substrate.

6 . The display panel according to claim 2 , wherein the active layer further comprises a twelfth active part connected between the first active part and the second active part;

wherein the second initial signal line comprises:

a main body line, wherein an orthogonal projection of the main body line on the base substrate extends along the first direction;

a second protrusion part, connected to the main body line, and an orthographic projection of the second protrusion part on the base substrate extends along a second direction, and the second direction intersects with the first direction,

wherein, an orthographic projection of the second protrusion part in the pixel driving circuit of a previous row on the base substrate at least partially overlaps with an orthographic projection of the twelfth active part in the pixel driving circuit of a current row on the base substrate,

wherein the second initial signal line further comprises:

a third protrusion part, connected to the main body line, wherein an orthographic projection of the third protrusion part on the base substrate extends along the second direction, and the orthographic projection of the third protrusion part on the base substrate is located on a side of the orthographic projection of the main body line on the base substrate away from the orthographic projection of the second protrusion part on the base substrate;

wherein, an orthographic projection of the third protrusion part in the pixel driving circuit of a previous row on the base substrate at least partially overlaps with an orthographic projection of the twelfth active part in the pixel driving circuit of a current row on the base substrate.

7 . The display panel according to claim 1 , wherein the orthographic projection of the first enable signal line on the base substrate is located between the orthographic projection of the second enable signal line on the base substrate and the orthographic projection of the first conductive part on the base substrate;

wherein the active layer further comprises:

an eighth active part, connected between the third active part and the fifth active part;

a ninth active part, connected to the fourth active part, wherein an orthographic projection of the ninth active part on the base substrate is located between the orthographic projection of the first enable signal line on the base substrate and the orthographic projection of the second enable signal line on the base substrate;

wherein the display panel further comprises:

a third conductive layer, located on a side of the first conductive layer away from the base substrate, wherein the third conductive layer comprises a first connection part, and the first connection part connects the eighth active part and the ninth active part through a via hole respectively.

8 . A pixel driving circuit, for driving a light-emitting unit, comprising:

a driving circuit, connected to a first node, a second node and a third node, configured to input a driving current to the third node through the second node according to a voltage signal of the first node;

a compensation circuit, connected to the first node, the third node and a gate driving signal terminal, configured to connect the first node and the third node in response to a signal of the gate driving signal terminal;

a control circuit, connected to the second node, a first power supply terminal, the third node, a first electrode of the light-emitting unit, and a first enable signal terminal, configured to connect the first power supply terminal and the second node in response to a signal of the first enable signal terminal, and configured to connect the third node and the first electrode of the light-emitting unit in response to the signal of the first enable signal terminal; and

a data writing circuit, connected to the second node, a data signal terminal and a second enable signal terminal, configured to transmit a signal of the data signal terminal to the second node in response to a signal of the second enable signal terminal,

wherein, during at least part of a period when the gate driving signal terminal outputs an invalid level, the first enable signal terminal alternately outputs a valid level and an invalid level, the second enable signal terminal alternately outputs a valid level and an invalid level, and a valid level period of the second enable signal terminal is within an invalid level period of the first enable signal terminal, and a valid level period of the first enable signal terminal is within an invalid level period of the second enable signal terminal.

9 . The pixel driving circuit according to claim 8 , further comprising:

a first reset circuit, connected to the first node, a first initial signal terminal and a reset signal terminal, configured to transmit a signal of the first initial signal terminal to the first node in response to a signal of the reset signal terminal;

a second reset circuit, connected to the first electrode of the light-emitting unit and a second initial signal terminal, configured to transmit a signal of the second initial signal terminal to the first electrode of the light-emitting unit in response to a control signal.

10 . The pixel driving circuit according to claim 9 , wherein the second reset circuit is further connected to the second enable signal terminal, and the second reset circuit is configured to transmit the signal of the second initial signal terminal to the first electrode of the light-emitting unit in response to the signal of the second enable signal terminal;

wherein the first reset circuit comprises:

a first transistor, having a first electrode connected to the first initial signal terminal, a second electrode connected to the first node, and a gate connected to the reset signal terminal;

wherein the second reset circuit comprises:

a seventh transistor, having a first electrode connected to the second initial signal terminal, a second electrode connected to the first electrode of the light-emitting unit, and a gate connected to the second enable signal terminal.

11 . The pixel driving circuit according to claim 8 , comprising:

a driving transistor, having a first electrode connected to the second node, a second electrode connected to the third node, and a gate connected to the first node.

12 . The pixel driving circuit according to claim 8 , wherein the compensation circuit comprises:

a second transistor, having a first electrode connected to the first node, a second electrode connected to the third node, and a gate connected to the gate driving signal terminal.

13 . The pixel driving circuit according to claim 8 , wherein the data writing circuit comprises:

a fourth transistor, having a first electrode connected to the data signal terminal, a second electrode connected to the second node, and a gate connected to the second enable signal terminal.

14 . The pixel driving circuit according to claim 8 , wherein the control circuit comprises:

a fifth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the first enable signal terminal;

a sixth transistor, having a first electrode connected to the third node, a second electrode connected to the first electrode of the light-emitting unit, and a gate connected to the first enable signal terminal.

15 . The pixel driving circuit according to claim 8 , wherein logic levels of the second enable signal terminal and the first enable signal terminal are opposite.

16 . The pixel driving circuit according to claim 8 , further comprising:

a storage circuit, connected between the first node and the first power supply terminal, wherein the storage circuit comprises:

a capacitor, connected between the first node and the first power supply terminal.

17 . The pixel driving circuit according to claim 8 , comprising:

a driving transistor, having a first electrode connected to the second node, a second electrode connected to the third node, and a gate connected to the first node;

wherein the compensation circuit comprises:

a second transistor, having a first electrode connected to the first node, a second electrode connected to the third node, and a gate connected to the gate driving signal terminal;

wherein the data writing circuit comprises:

a fourth transistor, having a first electrode connected to the data signal terminal, a second electrode connected to the second node, and a gate connected to the second enable signal terminal;

wherein the control circuit comprises:

a fifth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the first enable signal terminal;

a sixth transistor, having a first electrode connected to the third node, a second electrode connected to the first electrode of the light-emitting unit, and a gate connected to the first enable signal terminal;

wherein the pixel driving circuit further comprises a first reset circuit, a second reset circuit and a storage circuit;

wherein the first reset circuit comprises:

a first transistor, having a first electrode connected to a first initial signal terminal, a second electrode connected to the first node, and a gate connected to a reset signal terminal;

wherein the second reset circuit comprises:

a seventh transistor, having a first electrode connected to a second initial signal terminal, a second electrode connected to the first electrode of the light-emitting unit, and a gate connected to the second enable signal terminal;

wherein the storage circuit comprises:

a capacitor, connected between the first node and the first power supply terminal;

wherein, the driving transistor, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are P-type transistors.

18 . A display panel, comprising the pixel driving circuit according to claim 8 .

19 . A driving method of a pixel driving circuit, for driving a pixel driving circuit, wherein the pixel driving circuit is configured to drive a light-emitting unit and comprises:

a driving circuit, connected to a first node, a second node and a third node, configured to input a driving current to the third node through the second node according to a voltage signal of the first node;

a compensation circuit, connected to the first node, the third node and a gate driving signal terminal, configured to connect the first node and the third node in response to a signal of the gate driving signal terminal;

a control circuit, connected to the second node, a first power supply terminal, the third node, a first electrode of the light-emitting unit, and a first enable signal terminal, configured to connect the first power supply terminal and the second node in response to a signal of the first enable signal terminal, and configured to connect the third node and the first electrode of the light-emitting unit in response to the signal of the first enable signal terminal; and

a data writing circuit, connected to the second node, a data signal terminal and a second enable signal terminal, configured to transmit a signal of the data signal terminal to the second node in response to a signal of the second enable signal terminal,

wherein, during at least part of a period when the gate driving signal terminal outputs an invalid level, the first enable signal terminal alternately outputs a valid level and an invalid level, the second enable signal terminal alternately outputs a valid level and an invalid level, and a valid level period of the second enable signal terminal is within an invalid level period of the first enable signal terminal, and a valid level period of the first enable signal terminal is within an invalid level period of the second enable signal terminal,

wherein the driving method comprises:

in a first sub-stage of a first stage, the gate driving signal terminal and the second enable signal terminal outputting a valid level, and the first enable signal terminal outputting an invalid level;

in a second sub-stage of the first stage, the first enable signal terminal outputting a valid level, and the second enable signal terminal and the gate driving signal terminal outputting an invalid level;

in a second stage, the gate driving signal terminal outputting an invalid level, the first enable signal terminal alternately outputting a valid level and an invalid level, and the second enable signal terminal alternately outputting a valid level and an invalid level,

wherein, a valid level period of the second enable signal terminal is within an invalid level period of the first enable signal terminal, and a valid level period of the first enable signal terminal is within an invalid level period of the second enable signal terminal, and in the second stage, a level written to the second node by the data signal terminal is at least partially different from a voltage of the first power supply terminal.

20 . The driving method of the pixel driving circuit according to claim 19 , wherein the pixel driving circuit is applied to a display panel, and one frame period of the display panel comprises a picture updating period and a picture holding period;

in one frame period, first stages of all pixel driving circuits in the display panel are within the picture updating period, and second stages of all pixel driving circuits in the display panel are within the picture holding period.