Pixel circuit, display device including the same, and electronic device including the same
A pixel circuit includes: a first transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor comprising a gate electrode receiving a gate signal, a first electrode receiving a reference voltage or a data signal, and a second electrode connected to the first node; a third transistor comprising a gate electrode receiving a first emission signal, a first electrode receiving an initialization voltage, and a second electrode connected to a fourth node; a fourth transistor comprising a gate electrode receiving the first emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the second node; and a light-emitting element comprising a first electrode connected to the fourth node and a second electrode receiving a second power voltage.
1 . A pixel circuit comprising:
a first transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;
a second transistor comprising a gate electrode configured to receive a gate signal, a first electrode configured to receive a reference voltage or a data signal, and a second electrode connected to the first node;
a third transistor comprising a gate electrode configured to receive a first emission signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to a fourth node;
a fourth transistor comprising a gate electrode configured to receive the first emission signal, a first electrode configured to receive a first power voltage, and a second electrode connected to the second node;
a fifth transistor comprising a gate electrode configured to receive a second emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node;
a first capacitor comprising a first electrode connected to the first node and a second electrode connected to the third node;
a second capacitor comprising a first electrode connected to the first power voltage and a second electrode connected to the third node; and
a light-emitting element comprising a first electrode connected to the fourth node and a second electrode configured to receive a second power voltage.
2 . The pixel circuit of claim 1 , wherein
the first transistor comprises a first gate electrode connected to the first node and a second gate electrode configured to receive the first power voltage.
3 . The pixel circuit of claim 1 , wherein
the second transistor is configured to receive a reference voltage or a data signal through a single line.
4 . The pixel circuit of claim 1 , wherein
the first transistor, the second transistor, the third transistor, and the fifth transistor are N-channel metal oxide semiconductor (NMOS) transistors, and the fourth transistor is a P-channel metal oxide semiconductor (PMOS) transistor.
5 . The pixel circuit of claim 1 , wherein
the gate signal is a high signal at time points at which the second transistor receives the reference voltage and the data signal.
6 . The pixel circuit of claim 1 , wherein,
at a time point at which the light-emitting element emits light, the first emission signal is a low signal, and the second emission signal is a high signal.
7 . A display device comprising:
a scan driver configured to transmit a plurality of scan signals to a plurality of scan lines;
a data driver configured to transmit a plurality of data signals to a plurality of data lines;
an emission driver configured to transmit a plurality of emission signals to a plurality of emission control lines; and
a pixel unit comprising a plurality of pixel circuits, wherein each of the plurality of pixel circuits are configured to emit light according to a corresponding data signal to display an image,
the pixel circuit comprising:
a first transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;
a second transistor comprising a gate electrode configured to receive a gate signal, a first electrode configured to receive a reference voltage or a data signal, and a second electrode connected to the first node;
a third transistor comprising a gate electrode configured to receive a first emission signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to a fourth node;
a fourth transistor comprising a gate electrode configured to receive the first emission signal, a first electrode configured to receive a first power voltage, and a second electrode connected to the second node;
a fifth transistor comprising a gate electrode configured to receive a second emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node;
a first capacitor comprising a first electrode connected to the first node and a second electrode connected to the third node;
a second capacitor comprising a first electrode connected to the first power voltage and a second electrode connected to the third node; and
a light-emitting element comprising a first electrode connected to the fourth node and a second electrode configured to receive a second power voltage.
8 . The display device of claim 7 , wherein
the scan driver is configured to:
simultaneously transmit the scan signals to the plurality of pixel circuits in an initialization period and a compensation period; and
sequentially transmit the scan signals to the plurality of pixel circuits in a data writing period.
9 . The display device of claim 7 , wherein
the emission driver is configured to:
simultaneously transmit the first emission signal to the plurality of pixel circuits in an initialization period and a compensation period and to sequentially transmit the first emission signal to the plurality of pixel circuits in an emission period; and
simultaneously transmit the second emission signal to the plurality of pixel circuits.
10 . The display device of claim 7 , wherein
the first transistor comprises a first gate electrode connected to the first node and a second gate electrode configured to receive the first power voltage.
11 . The display device of claim 7 , wherein
the second transistor is configured to receive the reference voltage or the data signal through a single line.
12 . The display device of claim 7 , wherein
the first transistor, the second transistor, the third transistor, and the fifth transistor are N-channel metal oxide semiconductor (NMOS) transistors, and the fourth transistor is a P-channel metal oxide semiconductor (PMOS) transistor.
13 . The display device of claim 7 , wherein
the gate signal is a high signal at time points at which the second transistor receives the reference voltage and the data signal.
14 . The display device of claim 7 , wherein,
at a time point at which the light-emitting element emits light, the first emission signal is a low signal, and the second emission signal is a high signal.
15 . An electronic device comprising:
at least one memory;
at least one processor configured to execute an application stored in the at least one memory; and
a display module configured to process an image data signal and output image information,
wherein the display module comprises at least one pixel circuit,
wherein the at least one pixel circuit each comprises:
a first transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;
a second transistor comprising a gate electrode configured to receive a gate signal, a first electrode configured to receive a reference voltage or a data signal, and a second electrode connected to the first node;
a third transistor comprising a gate electrode configured to receive a first emission signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to a fourth node;
a fourth transistor comprising a gate electrode configured to receive the first emission signal, a first electrode configured to receive a first power voltage, and a second electrode connected to the second node;
a fifth transistor comprising a gate electrode configured to receive a second emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node;
a first capacitor comprising a first electrode connected to the first node and a second electrode connected to the third node;
a second capacitor comprising a first electrode connected to the first power voltage and a second electrode connected to the third node; and
a light-emitting element comprising a first electrode connected to the fourth node and a second electrode configured to receive a second power voltage.
16 . The electronic device of claim 15 , wherein
the first transistor comprises a first gate electrode connected to the first node and a second gate electrode configured to receive the first power voltage.
17 . The electronic device of claim 15 , wherein
the second transistor is configured to receive a reference voltage or a data signal through a single line.
18 . The electronic device of claim 15 , wherein
the first transistor, the second transistor, the third transistor, and the fifth transistor are N-channel metal oxide semiconductor (NMOS) transistors, and the fourth transistor is a P-channel metal oxide semiconductor (PMOS) transistor.
19 . The electronic device of claim 15 , wherein
the gate signal is a high signal at time points at which the second transistor receives the reference voltage and the data signal.
20 . The electronic device of claim 15 , wherein,
at a time point at which the light-emitting element emits light, the first emission signal is a low signal and the second emission signal is a high signal.