Conduction control circuit, display panel and display device

Inventors: Zhidong Yuan (Beijing, CN); Yongqian Li (Beijing, CN); Xue Dong (Beijing, CN)

Assignees: Hefei BOE Joint Technology, Co., Ltd.; BOE Technology Group Co., Ltd.; Beijing BOE Technology Development Co., Ltd.

G09G3/3266 G09G3/32 G09G3/3275 G09G2300/0408 G09G2300/0819 G09G2310/0267 G09G2310/0275 G09G2310/08 G09G2330/023

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Quick Facts

Patent No.: US 12711922
App. No.: 18/835,768
Granted: Aug 18, 2026
Kind: B2

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Abstract

A conduction control circuit includes: a gating control circuit, coupled to a first node, and configured to provide a signal of a first clock signal terminal to the first node in response to signals of a plurality of different gating control signal terminals; a control circuit, coupled to the first node and a second node, and configured to provide the signal of the first clock signal terminal or a signal of a first power supply terminal to the second node in response to a signal of the first node; and a conduction signal output circuit, coupled to the second node and a third node, and configured to provide a signal of a second clock signal terminal to a driving output terminal in response to a signal of the second node, and provide a signal of a first reference signal terminal to the driving output terminal.

Claims (20)

1 . A conduction control circuit, comprising: a gating control circuit, coupled to a first node, and configured to provide a signal of a first clock signal terminal to the first node in response to signals of a plurality of different gating control signal terminals; a control circuit, coupled to the first node and a second node, and configured to provide the signal of the first clock signal terminal or a signal of a first power supply terminal to the second node in response to a signal of the first node; and a conduction signal output circuit, coupled to the second node and a third node, and configured to provide a signal of a second clock signal terminal to a driving output terminal in response to a signal of the second node, and provide a signal of a first reference signal terminal to the driving output terminal in response to a signal of the third node.

2 . The conduction control circuit according to claim 1 , wherein the gating control circuit comprises: N gating control transistors; the N gating control transistors are in one-to-one correspondence with the plurality of different gating control signal terminals; a gate of an nth gating control transistor of the N gating control transistors is coupled to a gating control signal terminal corresponding to the nth gating control transistor; a first electrode of a 1st gating control transistor of the N gating control transistors is coupled to the first clock signal terminal; a second electrode of the Nth gating control transistor of the N gating control transistors is coupled to the first node; and the second electrode of the nth gating control transistor of the N gating control transistors is coupled to a first electrode of an (n+1)th gating control transistor of the N gating control transistors.

3 . The conduction control circuit according to claim 2 , wherein the control circuit comprises: a first control circuit, configured to provide the signal of the first clock signal terminal to the first node in response to a signal of a reset signal terminal; and a second control circuit, configured to provide the signal of the first clock signal terminal or the signal of the first power supply terminal to the second node in response to the signal of the first clock signal terminal and the signal of the first node.

4 . The conduction control circuit according to claim 3 , wherein the first control circuit comprises: a first transistor; wherein a gate of the first transistor is coupled to the reset signal terminal, a first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to the first clock signal terminal.

5 . The conduction control circuit according to claim 3 , wherein the second control circuit comprises: a second transistor and a third transistor; wherein a gate of the second transistor is coupled to the first node, a first electrode of the second transistor is coupled to the first clock signal terminal or the first power supply terminal, and a second electrode of the second transistor is coupled to a first electrode of the third transistor; and a gate of the third transistor is coupled to the first clock signal terminal, and a second electrode of the third transistor is coupled to the second node; wherein the second control circuit further comprises: a first capacitor; wherein a first electrode of the first capacitor is coupled to the first power supply terminal, and a second electrode of the first capacitor is coupled to the first node.

6 . The conduction control circuit according to claim 1 , wherein the conduction signal output circuit comprises: a first conduction transistor, a second conduction transistor and a second capacitor; wherein a gate of the first conduction transistor is coupled to the second node, a first electrode of the first conduction transistor is coupled to the second clock signal terminal, and a second electrode of the first conduction transistor is coupled to the driving output terminal; a gate of the second conduction transistor is coupled to the third node, a first electrode of the second conduction transistor is coupled to the driving output terminal, and a second electrode of the second conduction transistor is coupled to the first reference signal terminal; and a first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the driving output terminal.

7 . The conduction control circuit according to claim 6 , further comprising: a reset circuit, configured to provide a signal of a reset signal terminal or the signal of the first power supply terminal to the third node in response to the signal of the reset signal terminal; wherein the reset circuit comprises: a fourth transistor and a third capacitor; wherein a gate of the fourth transistor is coupled to the reset signal terminal, a first electrode of the fourth transistor is coupled to the reset signal terminal or the first power supply terminal, and a second electrode of the fourth transistor is coupled to the third node; and a first electrode of the third capacitor is coupled to the second electrode of the fourth transistor, and a second electrode of the third capacitor is coupled to the first reference signal terminal or a second reference signal terminal.

8 . The conduction control circuit according to claim 7 , further comprising: a third control circuit, configured to control the signal of the third node in response to the signal of the first node and the signal of the third node; wherein the third control circuit comprises: a fifth transistor, a sixth transistor, and a seventh transistor; wherein a gate of the fifth transistor is coupled to the first node, a first electrode of the fifth transistor is coupled to the third node, and a second electrode of the fifth transistor is coupled to a reset signal terminal; a gate of the sixth transistor is coupled to the second node, a first electrode of the sixth transistor is coupled to the third node, and a second electrode of the sixth transistor is coupled to the reset signal terminal; and a gate of the seventh transistor is coupled to the third node, a first electrode of the seventh transistor is coupled to the second node, and a second electrode of the seventh transistor is coupled to the first reference signal terminal.

9 . The conduction control circuit according to claim 8 , further comprising: a fourth control circuit, configured to control the signal of the third node in response to the signal of the first node, the signal of the second node, and the signal of the third node.

10 . The conduction control circuit according to claim 9 , wherein the fourth control circuit comprises: an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; wherein a gate of the eighth transistor is coupled to the first node, a first electrode of the eighth transistor is coupled to the third node, and a second electrode of the eighth transistor is coupled to a second electrode of the ninth transistor; a gate of the ninth transistor is coupled to the third node, and a first electrode of the ninth transistor is coupled to the first power supply terminal; a gate of the tenth transistor is coupled to the second node, a first electrode of the tenth transistor is coupled to a reset signal terminal, and a second electrode of the tenth transistor is coupled to the second electrode of the ninth transistor; and gate of the eleventh transistor is coupled to the second node, a first electrode of the eleventh transistor is coupled to the second electrode of the tenth transistor, and a second electrode of the eleventh transistor is coupled to the third node.

11 . The conduction control circuit according to claim 10 , further comprising: a fifth control circuit, configured to control the signal of the second node in response to the signal of the third node.

12 . The conduction control circuit according to claim 11 , wherein the fifth control circuit comprises: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; wherein a gate of the twelfth transistor is coupled to the third node, a first electrode of the twelfth transistor is coupled to a first electrode of a third transistor, and a second electrode of the twelfth transistor is coupled to a second electrode of the thirteenth transistor; a gate of the thirteenth transistor is coupled to the second node, and a first electrode of the thirteenth transistor is coupled to the first power supply terminal; a gate of the fourteenth transistor is coupled to the third node, a first electrode of the fourteenth transistor is coupled to a second reference signal terminal, and a second electrode of the fourteenth transistor is coupled to the second electrode of the thirteenth transistor; and a gate of the fifteenth transistor is coupled to the third node, a first electrode of the fifteenth transistor is coupled to the second electrode of the fourteenth transistor, and a second electrode of the fifteenth transistor is coupled to the second node.

13 . The conduction control circuit according to claim 12 , further comprising: a sixth control circuit, configured to control the signal of the third node in response to the signal of the first node, the signal of the third node, and a signal of a second power supply terminal.

14 . The conduction control circuit according to claim 13 , wherein the sixth control circuit comprises: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor; wherein a gate of the sixteenth transistor is coupled to the second node, a first electrode of the sixteenth transistor is coupled to a third reference signal terminal, and a second electrode of the sixteenth transistor is coupled to a first electrode of the seventeenth transistor; a gate of the seventeenth transistor is coupled to the second power supply terminal, a second electrode of the seventeenth transistor is coupled to the second power supply terminal; a gate of the eighteenth transistor is coupled to the first electrode of the seventeenth transistor, a first electrode of the eighteenth transistor is coupled to the third node, and a second electrode of the eighteenth transistor is coupled to the second power supply terminal; a gate of the nineteenth transistor is coupled to the first node, a first electrode of the nineteenth transistor is coupled to the first electrode of the eighteenth transistor, and a second electrode of the nineteenth transistor is coupled to a second reference signal terminal; and a gate of the twentieth transistor is coupled to the second node, a first electrode of the twentieth transistor is coupled to the third node, and a second electrode of the twentieth transistor is coupled to the second reference signal terminal.

15 . The conduction control circuit according to claim 14 , further comprising: a seventh control circuit, configured to control the signal of the second node in response to the signal of the second node, the signal of the third node, and a signal of a reset signal terminal.

16 . The conduction control circuit according to claim 15 , wherein the seventh control circuit comprises: a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a twenty-fifth transistor; wherein a gate of the twenty-first transistor is coupled to the third node, a first electrode of the twenty-first transistor is coupled to a second reference signal terminal, and a second electrode of the twenty-first transistor is coupled to a first electrode of the twenty-second transistor; a gate of the twenty-second transistor is coupled to the third node, and a second electrode of the twenty-second transistor is coupled to the second node; a gate of the twenty-third transistor is coupled to the second node, a first electrode of the twenty-third transistor is coupled to the first power supply terminal, and a second electrode of the twenty-third transistor is coupled to the first electrode of the twenty-second transistor; a gate of the twenty-fourth transistor is coupled to the reset signal terminal, a first electrode of the twenty-fourth transistor is coupled to the second reference signal terminal, and a second electrode of the twenty-fourth transistor is coupled to the first electrode of the twenty-second transistor; and a gate of the twenty-fifth transistor is coupled to the reset signal terminal, a first electrode of the twenty-fifth transistor is coupled to the second electrode of the twenty-fourth transistor, and a second electrode of the twenty-fifth transistor is coupled to the second node.

17 . A display panel, comprising: a display region and a non-display region; wherein the display region comprises: a plurality of sub-pixels, and each of the plurality of sub-pixels comprises a pixel circuit; the non-display region comprises: a timing controller, configured to provide a plurality of gating control signals; a plurality of conduction control circuits each according to claim 1 , coupled to the timing controller and the pixel circuit, wherein the plurality of gating control signal terminals are configured to receive the plurality of gating control signals, and the conduction control circuit is configured to provide a signal of the driving output terminal to the pixel circuit in response to the plurality of gating control signals provided by the timing controller.

18 . The display panel according to claim 17 , wherein the display region further comprises: a plurality of conduction signal lines, and pixel circuits in a column of sub-pixels are coupled to one of the plurality of conduction signal lines; and one of the plurality of conduction signal lines is coupled to the driving output terminal of one of the plurality of conduction control circuits.

19 . The display panel according to claim 17 , wherein the non-display region further comprises: a data driving circuit, coupled to the pixel circuit and the timing controller, and configured to provide a data signal to the pixel circuit in response to a data signal output by the timing controller; wherein the plurality of conduction control circuits are between the data driving circuit and the display region; or the plurality of conduction control circuits are on a side of the display region away from the data driving circuit.

20 . A display device, comprising: the display panel according to claim 17 .