IP Library › Granted Patent US 12711930
Granted Patent B2
US 12711930 · App. 19/021,963 · Granted Aug 18, 2026

Semiconductor device and electronic appliance

Inventors: Jun Koyama (Sagamihara, JP); Atsushi Umezaki (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G09G3/3677G09G3/3674G11C19/00H03K17/687H03K19/0013H03K19/018557H03K19/018571H10D30/6755H10D86/40H10D86/423H10D86/441H10D86/60H10D89/10G09G2310/0251G09G2310/0286G09G2310/0289G09G2310/08G09G2330/021
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Quick Facts
Patent No.
US 12711930
App. No.
19/021,963
Granted
Aug 18, 2026
Kind
B2
Abstract

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Claims (137)

1 . A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to the first wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the sixth transistor,

wherein a gate of the third transistor is electrically connected to a fifth wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,

wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a sixth wiring,

wherein a gate of the fifth transistor is electrically connected to the sixth wiring,

wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor,

wherein the gate of the sixth transistor is electrically connected to a fourth wiring,

wherein the first wiring is configured to output a first signal,

wherein the second wiring is configured to be a power supply line or a signal line,

wherein a first voltage is supplied to the third wiring,

wherein a second signal is supplied to the fourth wiring,

wherein a second voltage is supplied to the fifth wiring, and

wherein a third signal is supplied to the sixth wiring.

2 . The semiconductor device according to claim 1 ,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor have the same polarity.

3 . The semiconductor device according to claim 1 ,

wherein the second voltage is higher than the first voltage.

4 . The semiconductor device according to claim 1 ,

wherein a potential of the first wiring is increased when the second transistor, the third transistor, and the fourth transistor are off and the first transistor is on.

5 . The semiconductor device according to claim 1 ,

wherein the one of the source and the drain of the first transistor is directly connected to the first wiring,

wherein the other of the source and the drain of the first transistor is directly connected to the second wiring,

wherein the one of the source and the drain of the second transistor is directly connected to the third wiring,

wherein the other of the source and the drain of the second transistor is directly connected to the first wiring,

wherein the one of the source and the drain of the third transistor is directly connected to the gate of the first transistor,

wherein the other of the source and the drain of the third transistor is directly connected to the gate of the sixth transistor,

wherein the gate of the third transistor is directly connected to the fifth wiring,

wherein the one of the source and the drain of the fourth transistor is directly connected to the third wiring,

wherein the gate of the fourth transistor is directly connected to the gate of the second transistor,

wherein the one of the source and the drain of the fifth transistor is directly connected to the gate of the second transistor,

wherein the other of the source and the drain of the fifth transistor is directly connected to the sixth wiring,

wherein the gate of the fifth transistor is directly connected to the sixth wiring,

wherein the one of the source and the drain of the sixth transistor is directly connected to the third wiring, and

wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the second transistor.

6 . A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to the first wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the sixth transistor,

wherein a gate of the third transistor is electrically connected to a fifth wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,

wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a sixth wiring,

wherein a gate of the fifth transistor is electrically connected to the sixth wiring,

wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor,

wherein the gate of the sixth transistor is electrically connected to a fourth wiring,

wherein the first wiring is configured to output a first signal,

wherein the second wiring is configured to be a power supply line or a signal line,

wherein a first voltage is supplied to the third wiring,

wherein a second signal is supplied to the fourth wiring,

wherein a second voltage is supplied to the fifth wiring,

wherein a third signal is supplied to the sixth wiring, and

wherein a channel length of the third transistor is smaller than a channel length of the fourth transistor.

7 . The semiconductor device according to claim 6 ,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor have the same polarity.

8 . The semiconductor device according to claim 6 ,

wherein the second voltage is higher than the first voltage.

9 . The semiconductor device according to claim 6 ,

wherein a potential of the first wiring is increased when the second transistor, the third transistor, and the fourth transistor are off and the first transistor is on.

10 . The semiconductor device according to claim 6 ,

wherein the one of the source and the drain of the first transistor is directly connected to the first wiring,

wherein the other of the source and the drain of the first transistor is directly connected to the second wiring,

wherein the one of the source and the drain of the second transistor is directly connected to the third wiring,

wherein the other of the source and the drain of the second transistor is directly connected to the first wiring,

wherein the one of the source and the drain of the third transistor is directly connected to the gate of the first transistor,

wherein the other of the source and the drain of the third transistor is directly connected to the gate of the sixth transistor,

wherein the gate of the third transistor is directly connected to the fifth wiring,

wherein the one of the source and the drain of the fourth transistor is directly connected to the third wiring,

wherein the gate of the fourth transistor is directly connected to the gate of the second transistor,

wherein the one of the source and the drain of the fifth transistor is directly connected to the gate of the second transistor,

wherein the other of the source and the drain of the fifth transistor is directly connected to the sixth wiring,

wherein the gate of the fifth transistor is directly connected to the sixth wiring,

wherein the one of the source and the drain of the sixth transistor is directly connected to the third wiring, and

wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the second transistor.

11 . A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to the first wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the sixth transistor,

wherein a gate of the third transistor is electrically connected to a fifth wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,

wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a sixth wiring,

wherein a gate of the fifth transistor is electrically connected to the sixth wiring,

wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor,

wherein the gate of the sixth transistor is electrically connected to a fourth wiring,

wherein the first wiring is configured to output a first signal,

wherein the second wiring is configured to be a power supply line or a signal line,

wherein a first voltage is supplied to the third wiring,

wherein a second signal is supplied to the fourth wiring,

wherein a second voltage is supplied to the fifth wiring,

wherein a third signal is supplied to the sixth wiring, and

wherein the semiconductor device comprises a period in which a potential supplied to the fourth wiring and a potential supplied to the sixth wiring are inverted from each other.

12 . The semiconductor device according to claim 11 ,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor have the same polarity.

13 . The semiconductor device according to claim 11 ,

wherein the second voltage is higher than the first voltage.

14 . The semiconductor device according to claim 11 ,

wherein a potential of the first wiring is increased when the second transistor, the third transistor, and the fourth transistor are off and the first transistor is on.

15 . The semiconductor device according to claim 11 ,

wherein the one of the source and the drain of the first transistor is directly connected to the first wiring,

wherein the other of the source and the drain of the first transistor is directly connected to the second wiring,

wherein the one of the source and the drain of the second transistor is directly connected to the third wiring,

wherein the other of the source and the drain of the second transistor is directly connected to the first wiring,

wherein the one of the source and the drain of the third transistor is directly connected to the gate of the first transistor,

wherein the other of the source and the drain of the third transistor is directly connected to the gate of the sixth transistor,

wherein the gate of the third transistor is directly connected to the fifth wiring,

wherein the one of the source and the drain of the fourth transistor is directly connected to the third wiring,

wherein the gate of the fourth transistor is directly connected to the gate of the second transistor,

wherein the one of the source and the drain of the fifth transistor is directly connected to the gate of the second transistor,

wherein the other of the source and the drain of the fifth transistor is directly connected to the sixth wiring,

wherein the gate of the fifth transistor is directly connected to the sixth wiring,

wherein the one of the source and the drain of the sixth transistor is directly connected to the third wiring, and

wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the second transistor.