Non-volatile memory device, storage device including the same device, and method of operating the same storage device
A non-volatile memory device, a storage device including the non-volatile memory device, and an operating method of the storage device are provided. The non-volatile memory device comprises a data pin configured to output a data signal, and a command address pin being separate from the data pi the command address pin configured to receive a read command corresponding to the data signal and output a noise state data during a data output operation in which the data signal is output through the data pin in response to the read command.
1 . A non-volatile memory device comprising:
a data pin configured to output a data signal; and
a command address pin being separate from the data pin, the command address pin configured to,
(i) receive a read command corresponding to the data signal, and
(ii) output a noise state data through the command address pin during a data output operation in which the data signal is output through the data pin in response to the read command.
2 . The non-volatile memory device of claim 1 , wherein
the command address pin is configured to receive a noise monitoring command for the noise state data after receiving the read command and output the noise state data in response to the noise monitoring command.
3 . The non-volatile memory device of claim 2 , further comprising:
a register unit configured to temporarily store a noise index value for the noise state data,
wherein the non-volatile memory device is configured to output the noise state data based on the noise index value in response to the noise monitoring command.
4 . The non-volatile memory device of claim 3 , wherein
the noise state data comprises a flag bit corresponding to a noise detection status.
5 . The non-volatile memory device of claim 1 , further comprising:
a memory cell array including a first plane and a second plane different from the first plane,
a first page buffer corresponding to the first plane,
a second page buffer corresponding to the second plane, and
a control logic configured to collect the noise state data for the first plane and the second plane.
6 . The non-volatile memory device of claim 5 , wherein
the noise state data comprises a first noise state data for the first plane and a second noise state data for the second plane.
7 . The non-volatile memory device of claim 6 , wherein
the first page buffer is configured to perform the data output operation through the data pin, and
a read operation is performed in the second plane.
8 . The non-volatile memory device of claim 6 , wherein
the control logic is configured to output at least one of the first noise state data and the second noise state data to the command address pin during the data output operation.
9 . The non-volatile memory device of claim 6 , wherein
the control logic is configured to perform a noise detection operation on a first core voltage applied to the first page buffer and on a second core voltage applied to the second page buffer, and generate the first noise state data and the second noise state data.
10 . The non-volatile memory device of claim 1 , wherein
the non-volatile memory device is configured to perform the data output operation within a range of 10 us to 900 us, and
the non-volatile memory device is configured to perform an output operation for the noise state data within a range of 10 ns to 900 ns.
11 . A storage device comprising:
a first non-volatile memory device and a second non-volatile memory device connected to a first channel, the first non-volatile memory device and the second non-volatile memory device configured to perform a data input/output operation through the first channel; and
a storage controller configured to
provide a data input/output command for the data input/output operation to the first non-volatile memory device through a command address pin connected to the first channel,
perform the data input/output operation for the first non-volatile memory device through a data pin connected to the first channel, the data pin being different from the command address pin, and
receive a noise state data on at least one of the first and the second non-volatile memory devices in parallel with the data input/output operation through the command address pin.
12 . The storage device of claim 11 , wherein
the storage controller is further configured to output a noise monitoring command requesting the noise state data based on a ready/busy map, the ready/busy map including a first ready/busy state data for the first non-volatile memory device and a second ready/busy state data for the second non-volatile memory device.
13 . The storage device of claim 12 , wherein
the second ready/busy state data is configured to be updated through the command address pin during the data input/output operation.
14 . The storage device of claim 12 , wherein
the first non-volatile memory device is configured to perform the data output operation within a range of 10 us to 900 us, and
the second non-volatile memory device is configured to output the second ready/busy state data within a range of 10 ns to 900 ns.
15 . The storage device of claim 11 , wherein
when the first non-volatile memory device performs the data input/output operation and the second non-volatile memory device is in a busy state,
the storage controller is configured to output a noise monitoring command for the noise state data through the command address pin.
16 . The storage device of claim 15 , wherein
the storage controller is configured to provide the noise monitoring command to the second non-volatile memory device.
17 . An operation method of a storage device comprising:
providing a data input/output command through a command address pin;
performing a data input/output operation through a data pin different from the command address pin based on the data input/output command;
providing a noise monitoring command through the command address pin according to a condition during the data input/output operation; and
receiving a noise state data through the command address pin in response to the noise monitoring command during the data input/output operation.
18 . The operation method of the storage device of claim 17 , further comprising:
verifying the data input/output operation in response to the noise state data.
19 . The operation method of claim 17 , wherein
the condition is that
a plurality of non-volatile memory devices are connected to one channel to which the command address pin and the data pin are connected,
a first non-volatile memory device among the plurality of non-volatile memory devices performs the data input/output operation, and
the plurality of non-volatile memory devices except the first non-volatile memory device are in a busy state.
20 . The operation method of claim 17 , wherein
the condition is that
a plurality of planes are connected to one channel to which the command address pin and the data pin are connected,
a first plane among the plurality of planes performs the data input/output operation, and
the plurality of planes except the first plane are in a busy state.